Naveed Sherwani and his team at Open Silicon are developing solutions that ease the complex ASIC design and development process.

“Our data shows that ASIC reliability (defined as whether the chip works first time or not) is very low,” says the CEO Sherwani. “On an average about 30 percent of ASICs do not work the first time, and have to be re-spun. And on the predictability front, only 15 to 20 percent of chips are completed on time.

In any other industry—these numbers would not be acceptable,” he adds.

Sherwani speculates that this difference could be attributed to less maturity of the ASIC industry as compared to that of the automotive industry.

But overall, unlike the traditional ASIC vendor models, Open Silicon’s proprietary solution allows customers to make informed choices that lower cost and reduce risk at each step of the ASIC implementation process.

Its proprietary process begins with a systematic cost analysis that optimizes expenditures at each step in the supply chain. The company optimizes the chip supply chain through a wide portfolio of fabrication process technologies, pre-qualified IP, package assembly and test solutions and a design, product engineering and operations team.

Open-Silicon provides a complete solution, from package design and assembly to final test. The primary goal of Open-Silicon’s Product Engineering Group is to maximize the yield of chips from each wafer produced. They closely work with both the foundry engineers and the assembly house to address any process drift or changes that may cause yield issues.

Headquartered in Sunnyvale, CA the company was co-founded by Sherwani, Satya Gupta, and Scott Houghton.