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Evolving Scope of Power Reduction for a System-on-Chip
Somanath Viswanath
Friday, November 30, 2007
System designers and architects have been accustomed to making feature versus form-factor trade-offs for devices in the mobile product space. Users, however, demand a no compromise experience combined with an extended battery life. Reducing the power consumption of such products has gained sufficient importance to warrant an overhaul of existing System-on-Chip (SoC) design methodology.

Power reduction is one of the primary design constraints for the system architecture and implementation of SoC’s targeted for such products. The effective application of power reduction techniques necessitates the definition of a power specification, portfolio of power reduction techniques, suitable design infrastructure and a robust verification environment.

Developing a robust power specification

Device application and usage models are used by system architects to partition a system into its sub-components, define mission modes, and derive budgets for important design parameters for the system. These characteristics are documented in a functional specification of the system as well as in each component. This methodology should be extended to derive component level power budgets and define a design Power Specification.

Such a power specification is crucial to the successful application of power reduction techniques to a SoC. The specification must be comprehensive enough to enable the verification of the operation of a SoC in all of its mission modes. Designers must also be able to use this specification to verify the implementation of these techniques at each stage.

This specification makes clear the trade-offs and suitability of various power reduction techniques to be applied to a SoC.

Power reduction techniques and design infrastructure

Having a portfolio of power reduction techniques and their appropriate design support infrastructure is crucial to meeting the power budgets. A typical SoC will employ multiple power reduction techniques – each having its own implication on the physical realization of a SoC. In particular, the clock and power delivery networks must be aware of the requirements and stress imposed by these techniques.

System planning and architectural partitioning have the maximum impact on the factors that affect power consumption (Figure 1.0 for a list of power reduction techniques). For example, the device usage model dictates the activity levels of the logic as well as opportunities to reduce activity for applying clock gating techniques. The performance requirements dictate the selection of operating voltage and frequency for sub-units of the SoC. Architectural partitioning can be used to restrain routing of signals to minimize interconnect capacitance yielding dramatic reduction in dynamic power with a side benefit of a smaller die size.

Clock networks are a significant source of dynamic power consumption. Careful attention and proper placement of clock networks to reduce capacitance is important. One technique is to use custom clock buffers and manually route the clock nets to minimize their lengths. Clock gating applied at multiple levels of the clock network hierarchy has a dramatic impact on the dynamic power. Several EDA tools have functionality to detect opportunities for clock gating. However, comprehending the usage model reveals the best usage of this technique without increasing the overhead or degrading the skew of the clock network.

Current semiconductor fabrication technologies lead to the development of Multi-VT standard cell libraries that trade-off performance for reduced leakage Leakage power is a growing component of overall power consumption, especially at nanometer process nodes. Using a design methodology that takes advantage of such standard cell libraries can result in the usage of lower leakage cells that still meet performance requirements.

Customization of the physical implementation including development of custom cells, special placement and route techniques provides an additional reduction in interconnect capacitance. Careful routing of high-activity nets and logic is one such example. SoCs that are data-path intensive or routing intensive are suitable candidates for these techniques.

Some of the advanced power reduction techniques include creating a power island or a voltage island for functional units in the design. A power island permits an entire unit in the design to be powered down – eliminating both leakage and dynamic power. However, design changes are needed to implement this technique. For example, the state information of the unit that is powered down needs to be stored either in special ‘always on’ sections of this unit or saved to some external memory (on-chip or off-chip). Signal outputs from a powered down unit need to be kept at a logical value to prevent excessive power dissipation. The sequencing of clocks and power delivery to these power islands sometimes necessitates the development of special logic and state machines for their correct operation. The power to these islands can be turned off by either using dedicated off-chip voltage regulators or appropriately sized power switches supported in the process technology used to fabricate the SoC.

Voltage islands is a technique whereby the voltage supplied to a functional unit can be lowered while still meeting its performance requirement, the dynamic power being proportional to the square of the supply voltage results in significant savings even with minor voltage reductions. The surrounding interface logic should consist of voltage translators to electrically interface to the voltage island. Voltage islands can be enhanced to dynamically transition the operating voltage and frequency of a unit. This requires careful analysis to ensure that there are no timing violations and that the interface logic can handle such transitions.

The design infrastructure facilitating the application of these techniques includes standard cell libraries, memories, and other building blocks that are characterized under the operating conditions of interest. The libraries must include different flavors of interface logic, e.g., isolation cells, retention flip-flops, and level translators that are necessary for the application of these techniques.

The design methodology and tools must also support the analysis of the power savings resulting from the application of these techniques while accounting for any overhead due to its implementation. The verification and simulation environments must be sophisticated enough to model and verify the impact of these techniques at the appropriate level of detail.

Verification of power reduction techniques

The final aspect of the power reduction methodology is the verification of the implementation of the power specification for a SoC. The complex inter-play of mission modes with these power reduction techniques necessitates extensive verifications to ensure that the design meets the functional, timing, and electrical requirements.

The operation of the SoC must be verified in each of the mission modes, while the transitions between modes must also be functionally and electrically verified to ensure deadlock free operation.

Most SoC designs use an ad-hoc or precedent based criteria to select a power reduction technique. However, the design methodology must include analysis and feedback steps to determine the true savings from these techniques in the intended operating environment. For e.g., the dynamic power saving from the application of a voltage island is proportional to the amount of time spent in the lower supply voltage state, offset by the power consumed in level shifting interface cells.


An effective power reduction methodology starts with the creation of a power specification document that takes advantage of the product usage patterns, system partition, and derives power budgets for sub-components.
A rich portfolio of power reduction techniques with a supportive design infrastructure is necessary in order to tackle constraints to reduce power. A rigorous approach to determine the ‘true’ efficacy of these methods should also be a part of the design flow.
Architecture-level power optimizations and multiple power reduction techniques enable SoC designers to meet aggressive power budgets resulting in feature-rich devices that provide the desired end-user experience while minimizing power consumption.

The author is Director of Technical Marketing insilica. He can be reached at somanath@insilica.com

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