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February - 2003 - issue > Cover Feature
3D Chips Future Possibilities
Vivek Subramaniam
Thursday, January 30, 2003
OVER THE LAST TWO DECADES, THERE HAS BEEN sustained interest among researchers in the development of a “3D” circuit, namely, a chip technology with multiple layers of transistors stacked over each other (unlike conventional chips, in which transistors are packed in a single plane only). Such an approach would dramatically reduce the chip area, since transistors could now be packed in all three dimensions. Proponents of 3D integration believe that the price of a given chip will fall, since chip costs generally increase with increasing die area. Additionally, it is believed that chips made with 3D technology will have increased speed, since the delay associated with a signal traveling along an interconnect across a chip is often a large fraction of the switching speed of a transistor. By folding the chip over, the average length of the interconnects is reduced (since the chip area is reduced).

Several recent developments have occurred in industry that makes an overview of 3D technology worthwhile. In 2001, Santa Clara, CA-based Matrix Semiconductor, Inc., announced that it was ramping up for production of the world's first commercially available 3D chip technology. Based on the benefits of 3D technology, Matrix claims that it will offer a tremendous cost advantage over its 2D competitors. Subsequently, other companies have also indicated that they are investigating the potential for 3D chip technology.

The transistors in essentially all chips currently on the market are manufactured in only one level for a simple reason—the crystalline silicon wafer can be accessed only "once" during the process. After a layer of transistors is built and passivated, the wafer is completely coated by an insulating layer of silicon dioxide, an amorphous material. It is impossible to grow crystalline silicon on top of this layer. Any subsequent deposition of silicon will result in the formation of polycrystalline or amorphous silicon, which has substantially worse electrical properties.

To get around this problem, various creative solutions have been devised, the most obvious of which is to build transistors in polycrystalline silicon. This is actually a well-known art—the pixel transistors in virtually all liquid crystal displays are fabricated in amorphous or polycrystalline silicon. By carefully controlling the structure of the polycrystalline silicon using techniques such as metal induced lateral crystallization (MILC), various researchers have successfully built fairly high performance transistors in this material. Furthermore, some have actually succeeded in forming crystalline silicon over the silicon dioxide surface using a technique known as epitaxial lateral overgrowth (ELO), in which the crystalline silicon is essentially grown over SiO2 by growing it out and over from a window cut down through the SiO2 layer to the underlying silicon wafer.

There is a problem though—all of these possible solutions use relatively high temperatures to fabricate additional levels of transistors. Silicon is usually deposited above 500°C. The high temperatures steps (dopant activation, gate oxidation, and silicidation) needed to fabricate the second level of transistors would be as high as 1000°C. These temperatures are so high that any transistors on “lower” levels would be destroyed or severely degraded, as would the metal lines interconnecting them. While techniques such as MILC substantially reduce the temperatures needed to fabricate devices, much work remains to be done to produce a fully 3D-compatible transistor fabrication technology. This limit, often called the “thermal budget” limit, is a serious challenge to achieving 3D using this sequential building approach.

An alternative approach to 3D that eliminates this problem has been proposed, and in fact was the technique used by IBM in their recent presentation. The individual layers of transistors are built on separate wafers and then bonded together to produce a 3D chip. Since the layers are built separately, there are fewer thermal budget constraints, and the individual layers of transistors can be fabricated using tried and true 2D transistor fabrication processes.

Unfortunately, there are substantial problems with this approach as well. Simply bonding the two layers together does not produce a 3D chip; the transistors on the individual layers must be interconnected to produce functional circuits. The accuracy of aligning the two layers and then bonding them is extremely poor. This limits the achievable interconnection pitch, since the interconnects must be designed to make contact to devices on different layers in spite of worst-case offsets between layers. This is a major problem, since modern chip sizes are often limited by the density of interconnects, rather than by the size of the transistors.

Chip size vs. cost:
Clearly, there is a net win in going to 3D from the standpoint of chip size. Does this correspond to a reduction in cost? The answer is, unfortunately, in many cases, no. One of the major parameters that affects chip cost is yield. The percentage of chips that work within acceptance specifications is called the yield. Not all chips that are actually fabricated work, or work at the clock speed for which they were designed to work. Even in mature fabrication processes, this number is often no more than 90%. The yield of a chip goes down for every additional process step. Therefore, when we compare a 2D chip to a 2 layer 3D chip, we find that the yield for the 3D chip will probably be worse than that of the 2D chip, raising its cost. This is because the 3D chip took twice the number of steps to build than the 2D chip. If the yield of every additional layer of transistors is 90%, by the time we have reached five layers, we are down to a net yield of only 60%, which significantly impacts cost.

Speed issues:
It is true that interconnect delay is a significant factor in limiting chip speed. However, creative techniques employed by circuit designers have substantially mitigated this problem. Critical circuit blocks are interconnected using low-resistance lines, reducing the signal delay between them. Additionally, placing repeaters along the critical signal path, which boost the signal strength, can increase the speed of signal transfer. The net result is that this problem is not quite as bad as it initially seemed, and therefore, it is not clear that 3D will make sense from this perspective alone.

When would 3D chips be attractive?
There are two situations in which 3D chips may be attractive. First, if the complexity of additional layers is substantially lower than the complexity of the first layer, then the decrease in yield might not be so bad, and the cost benefits that result from the reduced die size may actually outweigh the yield loss. Analyzing the Matrix 3DM™ process, this is the case. The 3DM™ chip consists of multiple layers of memory cells stacked over a silicon chip that provides the addressing, decoding, etc. The memory cells themselves consist of no transistors; rather, they consist of diode/antifuse arrays that are very simple to build and require only a few process steps per layer (see figure). The transistors, which require many more process steps, are only built on the lowest layer. Hence, the incremental yield loss (and therefore, the incremental cost) of additional layers is quite small, resulting in a net cost advantage for the chip over more conventional 2D memories.

The second situation when 3D chips may be attractive is in “System on a Chip (SoC)” or heterogeneously integrated system applications. In these applications, multiple fabrication technologies are needed within the same system. For example, an SoC may have memories for storage, fast transistors for computation, and optical components for communication. Integrating these on a single chip in a 2D fashion is complicated enough that a bonding-based 3D approach, in which the individual types of devices are fabricated separately, may offer substantial advantages. Furthermore, since the interconnections between these devices will be relatively sparse (for example, at the edge of a large memory array or a large processor block), the density penalty imposed by the bonding process will likely not be a serious constraint.

Given these potential opportunities, are there viable business opportunities for the large corporation or the small startup company? The answer is a resounding—it depends! With the trend toward fabless semiconductor outfits, where most of the manufacturing is done at a “for-hire” foundry, 3D is a harder sell since many of these foundries are not willing to deal with the additional process development required to achieve this. The success is predicated on its ability to achieve 3D without requiring any unusual process steps. However, with the general trend towards increasingly complicated SoC development, it is likely that 3D will continue to be an attractive “technology of the future,” albeit with highly specific and compartmentalized uses.

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