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Sequence Design: Enabling energy efficient SoC design

Pradeep Shankar
Saturday, July 12, 2008
Pradeep Shankar
This is the equation that Vic Kulkarni’s professor at IIT Bombay taught him while studying microelectronics. The significance of the equation, which represents the power dissipation for a digital circuit, didn’t really matter to him while studying as much as it matters today: His company, Sequence Design, is built around this equation.

In fact, the equation dominates all of the chip design that’s happening across the world as well. With the insatiable demand for functionalities from chips—in wireless, gaming, graphics, mobile computing, and so on—the complexity has gone up. The semiconductor industry has reactively moved from 180nm to the 90nm fabrication. If one were to unwind all the interconnect wires and metal layers of a latest processor, and lay them out in a straight line, it would stretch out to more than a mile. Imagine all of that sitting on a chip. This lump of copper is bound to create trouble. As a metal, heat generation is expected.

It isn’t just feature size reduction anymore, as the laws of physics have now become very critical. Power, timing, cross-talk effects, and heat have become very tall hurdles, which cannot be solved without tackling the silicon effects. “The laws of physics are helping Sequence grow,” says Kulkarni.

For nearly two decades, the EDA industry has been missing the fundamental components of power management. Until now, power analysis of a design was done utilizing tools that report power consumption of a design at various stages of the design cycle. This method generally results in costly design rework “spins.” Today’s designs require power optimization tools that address power consumption early in the design cycle and reduce time to market. Conventionally, design tools were algorithm driven and the silicon effects were approximated. Now the game is changing.

Previously performance and area were the critical factors. Now, power has become critical. For many companies ‘power’ defines the growth and the profitability of the company. With the high frequency devices and smaller geometries driving the handset markets, standby power is another looming issue. “Currently, the leakage eats up nearly 30 percent of the battery,” says Kulkarni. “This is a tremendous opportunity for us, as there are no tools in the market.”

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Reader's comments(5)
1:this is a very good article
Posted by: - 17th Jun 2007
2:this is a nice article
Posted by: - 17th Jun 2007
3:this is a very informative article.
Posted by: - 17th Jun 2007
4:very nice article
Posted by: - 17th Jun 2007
5:Very good article
Posted by: - 14th Jun 2007
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