Sequence Design: Enabling energy efficient SoC design
Date: Saturday , July 12, 2008
This is the equation that Vic Kulkarni’s professor at IIT Bombay taught him while studying microelectronics. The significance of the equation, which represents the power dissipation for a digital circuit, didn’t really matter to him while studying as much as it matters today: His company, Sequence Design, is built around this equation.
In fact, the equation dominates all of the chip design that’s happening across the world as well. With the insatiable demand for functionalities from chips—in wireless, gaming, graphics, mobile computing, and so on—the complexity has gone up. The semiconductor industry has reactively moved from 180nm to the 90nm fabrication. If one were to unwind all the interconnect wires and metal layers of a latest processor, and lay them out in a straight line, it would stretch out to more than a mile. Imagine all of that sitting on a chip. This lump of copper is bound to create trouble. As a metal, heat generation is expected.
It isn’t just feature size reduction anymore, as the laws of physics have now become very critical. Power, timing, cross-talk effects, and heat have become very tall hurdles, which cannot be solved without tackling the silicon effects. “The laws of physics are helping Sequence grow,” says Kulkarni.
For nearly two decades, the EDA industry has been missing the fundamental components of power management. Until now, power analysis of a design was done utilizing tools that report power consumption of a design at various stages of the design cycle. This method generally results in costly design rework “spins.” Today’s designs require power optimization tools that address power consumption early in the design cycle and reduce time to market. Conventionally, design tools were algorithm driven and the silicon effects were approximated. Now the game is changing.
Previously performance and area were the critical factors. Now, power has become critical. For many companies ‘power’ defines the growth and the profitability of the company. With the high frequency devices and smaller geometries driving the handset markets, standby power is another looming issue. “Currently, the leakage eats up nearly 30 percent of the battery,” says Kulkarni. “This is a tremendous opportunity for us, as there are no tools in the market.”
Kulkarni and his team at Sequence are tackling the low-power design challenge. The tools, Sequence offers, are potentially a paradigm shift in the way power is looked at in a design.
No Bullets, Only Numbers
There are no magic bullets to solve the power problem. The semiconductor design landscape is changing so rapidly that you find Kulkarni always globe trotting—meeting customers, academic researchers and standards defining experts—to get the pulse of the market. Last year, he figured out the three magic numbers, which he says captures the spectrum of today’s worldwide consumer products in terms of wattage.
On the handheld battery side, three watts is the magic number because the human hand gets uncomfortable with that after 10 minutes or so. Many hand-held device manufacturers are scrambling to be below the 2.6-watt number so that there is enough cushion before hitting three watts. Many applications developed these days for the handset market are in that range of 2.6 and 2.8 watts.
For many of the consumer gadgets other than the handhelds, six watt is the magic number. At that level, flat-pack-plastic-package, which is cheaper, has to be replaced by a PPGA [plastic pin grid array] and there is a gross margin issue of power. This increases the cost of the unit by almost $1. For a consumer application, a $1 increase is killing of your gross margins.
The next threshold is 10 watts, which is critical while designing large ASIC chips application such as high-end graphics. Many designers would ideally like their chip designs to be in the range of 9.5 to 9.6 watts. Beyond 10 watts, PPGA has to be converted into flip chip in order to manage the heat. This would mean an additional $1.50 per part. If you are making millions of chips, it turns out to be an expensive proposition.
The Holistic Approach
Understanding the design needs for the consumer space in terms of wattage, has made Sequence’s team to look at the problem of power more holistically. “Power has to be managed at all levels of abstraction. It has to be managed at the micro-architecture level all the way to the final sign-off. When you talk to companies like Samsung, Sony, Qualcomm and Nokia you hear that power management is extremely difficult,” says Kulkarni.
Recently, one of Sequence’s customers, who were designing a complex mass-market SoC, discovered late in the design cycle that process and library decisions made to reduce power resulted in an inability to close timing due to silicon-integrity effects. This in turn significantly increased overall design time, causing them to almost miss their market window.
Kulkarni reiterates not to look at such issues, or at certain points in the process, in isolation. All must be considered together as interdependent effects, consistently throughout the design cycle, and tools performing analysis at a high level must consider their impact on subsequent steps in the process. Just as vital, power-aware tools in the flow must share simple things such as common timing engines and language so that a change in timing, for instance, doesn’t affect SI (signal-integrity).
“The key to designing power-efficient devices is a holistic approach to power-aware design,” says Kulkarni. The most successful chips—those built in the shortest time with the lowest power—will have contemplated all the issues having to do with power at the very beginning, and carried that spirit of analysis all the way through to tape-out. But power reduction is only part of the equation. It is essential to possess a deep understanding of physical effects that give rise to power consumption as well as power considerations on other parameters such as reliability, timing, SI and cost.
As we get to smaller feature size, standby leakage power increases exponentially. Transistors start leaking power when they are not supposed to. Even when the mobile phone or camera is switched off or on standby, there is tremendous power leakage. This calls for recharging of the device.
Power leakage is an enormous problem at 90nm, growing exponentially with the rapid migration to subsequent process nodes. Also, at the physical level, SI effects become more prominent at finer line widths due to the increased coupling capacitances employed with low-power design techniques such as voltage islands and multiple threshold voltages. This combination makes closing timing on low-power designs increasingly difficult and time consuming particularly if timing, power, and SI are not handled concurrently.
Kulkarni understands these challenges. The tools that Sequence offers addressess these concerns.
The Global Footprint
The Santa Clara, CA-based company maintains “Centers of Excellence,” consisting of sales, support, and R&D facilities in the U.S., Japan, and India, giving it true worldwide reach. “With these Centers, I don’t think Sequence really has a traditional headquarter anymore – it’s wherever I happen to be at a moment, talking to and learning from our product teams all over the world,” says Kulkarni, the President and CEO of the company.
In the past five years, Sequence has invested over $4.5 million in its Noida, India-based R&D operations alone. While the engineers in India work on mission-critical technology contributions in the area of low power, Kulkarni has instituted a “Made in India” program that promotes homegrown development from ground up for new tools and technologies. In India, the company has a growing customer base of multinational semiconductor companies, particularly in Bangalore’s technology-rich environment.
All great technologies do not translate into sales if one is not reaching the right customers, and Kulkarni is aware of this. He has built a strong global sales, marketing, R&D, and customer support powerhouse to spread his low-power message.
In 2006 the company’s bookings grew nearly 20 percent and Sequence added 15 new customers to its global roster. Today, Sequence design tools are in use at nearly all of the top semiconductor companies worldwide, and in more than 150 companies. Some of its marquee clients include IBM, LSI, and Broadcom.
In order to spread the awareness of low-power design, last year, Sequence conducted a series of technical seminars in India, Japan, and Korea. These events have attracted top designers from leading companies, and featured speakers from leading academic and corporate realms in the host countries.
Kulkarni says, “We invested time and effort to educate and convince prospective customers about the need for power management tools. All these years it was a ‘missionary sale.’ Things are changing. These days I don’t need to do missionary selling anymore. Customers, themselves call us and ask how we could help them reduce. We will benefit from the evolving market,” says Kulkarni.
Sequence has focused on low-power design from the earliest days of the company. “Our success is due to the fact that we did not become distracted by fads, or lose focus. We knew a significant challenge was coming and we prepared for it well ahead of our competitors, and even some of our customers!” says Kulkarni.
In order to quickly take advantage of the emerging global opportunity, the key challenge for companies like Sequence will be to expand the workforce and most importantly applications engineering and support. The quicker it creates that workforce, the faster it will pay off. However, Kulkarni believes it is not necessary to create one’s own workforce. “Collaboration is the way to go forward,” he says. Sequence has established relationships with other complimentary partners such as design service companies, and companies that offer other product lines such as electronic system level (ESL). “Through such partnerships, our products become lynchpin of their design flows. And with this we can offer bigger solutions to our customers as quickly as possible without significant burden of hiring a lot of people,” says Kulkarni.
While the company had formalized relationships with 10 different companies, in the coming year Kulkarni wants to focus on entering into design center agreements with other partners, so that it can offer combined solution with custom consulting knowledge for reducing power.
Kulkarni’s penchant for Physics indicates he is confident Sequence is up to the challenges presented by the shrinking size of the chip. His aim is to capture the complex, yet fundamental, link between the functional, electrical, thermal, and mechanical aspects of power management. He is confident to continue to introduce better and more sophisticated products for low-power design, calling on its global R&D workforce, and partnering with the world’s leading designers and manufacturers to supply the necessary intellectual capital.
The Early Days
Vic Kulkarni discovered a passion for electronics at a young age, helped in part by a couple of mentors, one of who was among the country’s brightest young inventors and responsible for introducing him to transistors. Then on Kulkarni quickly learned how to build simple radios for all of his relatives.
His passion took him to IIT Bombay to study Microelectronics. “It was there for the first time I held Andy Grove’s solid state physics book, which was a bible for all solid state electronics folks around the world. It was quite fascinating to learn a brand new science and understand transistors in silicon,” recalls Kulkarni.
After IIT, Kulkarni had his pick of post-graduate schools all over the world, and chose the University of Cincinnati because of its emphasis on solid-state electronics, all the rage in the mid-‘70s.
After college, Kulkarni landed his first job at National Semiconductor back in the days when Silicon Valley had more orchards than semiconductor fabs, and high-tech legends like Charlie Sporck, Jerry Sanders, and Gordon Moore were still making their mark.
In 1999, Kulkarni, a veteran in the semiconductor and EDA space joined a startup called Frequency Design which had some excellent knowledge in the interconnect science. Perceiving the opportunity in power management and heat control tools for chip design, Kulkarni quickly acquired a couple of other startups in these spaces and Sequence Design came into existence.
Kulkarni recalls the challenges he faced when taking the helm at Sequence: “When I came to the company we began merging three disparate concerns into one, creating the present company. To effectively integrate and manage these entities, I set about shifting employees from one division to another– it’s important not to create ‘silos’ of knowledge or business practices, otherwise you never form a new corporate culture.
“As a next generation EDA tools company, we are marrying quantum physics, computer science and electrical engineering to derive new tools for the submicron chip market,” says Kulkarni. “From experience with the traditional approach, it is clear that algorithmic and architectural design decisions have the greatest influence on power consumption. Therefore, any new methodology must start at this system level.”
Before becoming Sequence’s CEO, he served as chief operating officer for two years, setting the company’s vision and delivering power and signal-integrity products for nanometer systems-on-chip design. Prior to joining Sequence, he was general manager and vice president of Avant!’s Silicon Business Unit, responsible for Silicon IP and Process Modeling tools, as well as creating a “success template” for a series of high-profile mergers. Coincidentally, he came to Avant! after his company Meta-Software, where Kulkarni served as vice president of worldwide marketing, was acquired. While at Meta, he helped lead a highly successful IPO, establishing the company with a $160 million market cap.
The Cool Tools for Hot Chips
Sequence’s flagship product, PowerTheater, analyzes and optimizes power at RTL, where decisions are made that determine 80 percent of a chip’s total power budget, leading to better results and faster time to market. “PowerTheater helps us manage, estimate, and reduce power when it counts: at RTL, pre-synthesis,” said Sanjay Kasturia, co-founder, CTO & chairman of Teranetics, one of Sequence’s customers. “Early power exploration of various architectures is critical to our success in low-power design.”
PowerTheater is the industry standard for low-power design, with capabilities ranging from early RTL analysis to full-chip power estimates for today’s largest designs. PowerTheater allows users to begin the design process with a firm handle on power budgets – before synthesis, when it is too late to optimize – and complete projects with verified results that correlate to silicon. It also allows designers to inspect and probe the precise areas where power is being wasted.
Sequence recently enhanced PowerTheater for the challenges of 65nm design, adding a range of “silicon-aware” features that produce more accurate results, and adding support for multi-voltage designs along with enhanced power-saving techniques.
The 2006 EE Times EDA Users Survey revealed that most chip designers believe managing leakage current will become their biggest concern as feature sizes shrink.
So naturally, managing leakage has become a priority for Sequence, and its CoolPower products are breaking new ground in this regard. For example, a recent announcement the company made with Dongbu Electronics, a leading Korean chip foundry, disclosed a remarkable 240X reduction in leakage currents with a jointly developed, CoolPower design flow. “Sequence’s leadership in low-power design tools and its particular expertise in leakage power makes it an ideal partner for this effort, as demonstrated by these outstanding results,” said Dr. Jae Song, Dongbu Electronics’ executive vice president of marketing.