SONET, the undisputed king of bandwidth continues to reign over the carrier space. Currently, data networks in the metro are transported through TDM circuits, like SONET, which are based on point-to-point, fixed bandwidth connections most appropriate for voice and constant bit rate services. But one should know that today’s metro networks are themselves in a mess. In fact this overcapacity in the synchronous optical network (SONET) communications infrastructure pushed Global Crossing Inc. into bankruptcy in 2002.

As carriers and some of the large enterprises with their own Sonet networks, begin to fill up their pipes, some are realizing they can clear more space by packing their traffic tighter using new standard, which can save them the expense of buying more capacity.

Resilient Packet Ring (RPR) seems to be the solution to the bandwidth bottleneck. It can drastically improve fiber efficiency. RPR is not a wholly newfound standard; rather it combines the best of both—Ethernet and Sonet—with many additions of its own. These additional functions help in making it an extremely attractive alternative to either Sonet or Ethernet for the high-speed, convergent, multimedia network.

Like Sonet, RPR operates within rings. But RPR differs from Sonet in how traffic is placed onto the rings. In most Sonet setups, traffic flows in only one direction around the ring; RPR lets traffic be provisioned in both directions, thereby doubling the amount of traffic that can traverse the rings. Data is taken off the ring at its destination, which keeps the maximum amount of bandwidth between nodes available at all times.

Before RPR can benefit from widespread use, standards need to be developed that facilitate interoperability among multiple vendors and across international boundaries. The work is already in progress. The IEEE created a draft specification for RPR and is expected to ratify the standard this year. If this materializes then it could actually improve the bandwidth efficiency, control latency and jitters and can also increase the efficiency of data traffic.

Ever since the standards body initiated the process, the interest in RPR has remained strong. The vendor-side is dominated by traditional OEMs like Nortel, Cisco and start-ups like Luminous, Lantern and Corrigent, and the silicon vendors like Infineon and Alliance Semiconductor, all running behind to have play in the RPR space. With the basic spec of the RPR standard, chipmakers forayed into designing the RPR media access control (MAC) chip with a hope that carriers will more readily buy the equipment because the technology is not proprietary.

For the last two years companies like Infineon and Alliance Semiconductors have been engaged in the design of RPR MAC silicon. “To stay on par with the emerging trends, we need to build technology even before it is standardized,” explains Nirmal Saxena, VP Architecture & Engineering, Alliance Semiconductors.

Designing chips for future is like walking on tight rope. If your target is clear, so is your success, but a bit of miscalculation can get you down instantly. Technology professionals like Saxena understand the risks involved. But they cannot sit and watch, because “a chip takes 18 months to be manufactured, if we try developing silicon after the standardization we are losing time and money. And our competitors will be surely ahead of us and we will loose the market window,” says Saxena.

Saxena and his team have tackled the tricky situation quite well. They have weighed the pros and cons of each of the three approaches to design an integrated chip— programmable silicon (processors), reconfigurable silicon (FPGA) and fixed silicon (ASIC).

Reconfigurable silicon or the FPGA’s are like the tiled structures from which the chip can be manufactured to perform multiple tasks. Its hardware flexibility and high degree parallelism are unmatchable, but it has low clock-rate and requires huge investment. The costs are high because the amount of function you can do on a single piece of silicon will be limited. Because of this generality the silicon size is big. And traditionally in the silicon industry, if the die size is big, the yields are low and cost of manufacturing goes high.

Processors have high clock rate. The software flexibility they offer is commendable and most importantly, it needs low investment. On the downside, they do not offer the parallelism those communication applications like packet processing call for.

ASICs offer high parallelism. It isn’t expensive to design an ASIC. The flipside is it offers very low flexibility, which would mean if a particular standard or protocol changes the previously designed ASIC has to be thrown away.

Saxena was looking forward to architect the RPR silicon using adaptive computing technology. Such a chip required to offer high flexibility, high parallelism, high clock rate and yet the costs had to be low. Flexibility was required because it gives the system designer various advantages—faster design time, faster time-to-market, ability to fix hardware bugs and administration of functionality upgrades. So Saxena’s team went about designing a chip that stays as close to ASIC like fixed silicon and just adds enough flexibility to address target RPR applications. “Such an approach allows the chip to maintain ASIC-like cost and performance benefits while offering the flexibility to address target application needs. Even if RPR doesn’t take off, this silicon will find applications still usable,” says Saxena.

The fact that Saxena has been able to architect an adaptive computing chip enables him to either accommodate changes in the standard without requiring a silicon re-spin or facilitate timely migration to a new silicon spin if the ratified standard requires unanticipated changes.

This complex chip architecture (0.13 micron, 5 million gates and 4MB memory, 20 gbps interface) was in a short span of two years. “More than the chip being adaptive what is satisfying is the fact that the engineers in our design center in India were able to do a large chunk of the design and the designed chip worked the very first time,” says Saxena. Even large design houses take seven to eight versions of silicon to get the architecture right.

Now that Saxena has been successful in seeing the adaptive computing RPR silicon to its fruition, its adoption in enterprise networks remains a big question. Widespread corporate adoption of RPR will help usher in the cost-effective transport of popular Ethernet and IP communications services. RPR transport will provide efficient bandwidth protection, accommodate breaking data traffic and provide the quality of service needed for these advanced packet applications.

Silicon vendors who initially embraced RPR and set about architecting solutions should note that today RPR is growing at a phenomenal rate. Michael Howard, principal analyst of Infonetics Research points out in his latest report, “Worldwide RPR revenue hit $323 million in 2003, and we project it to grow 200 percent to $967 million by 2007, a CAGR of 32 percent.” The report also states that service providers in North America and Europe are figuring in RPR over SONET/SDH plans much more now than they were even six months ago. Good news for Saxena and his like.