As the semiconductor industry marches down the path prescribed by Moore’s law, the next hurdle in this path is expected to be the 90nm process. The industry had a somewhat traumatic experience with the 130nm technology node, where the switch to Copper metallization and lower dielectric constant (Low-k) inter-metallic oxides caused a lot of hiccups during the initial ramp-up of this technology. With all the 130nm issues resolved, the adoption of the 90nm process presents unique challenges to chip designers and design companies. There are both technical challenges as well as business challenges associated with the transition to 90nm, especially for fabless companies.

Technical Challenges
Andy Grove gave a note of warning at the IEDM conference in December 1992, “Power consumption, particularly off-state current leakage, is the major technical problem facing the semiconductor industry.” The leakage power of an average System-On-Chip (SOC) design in 90nm is expected to be roughly equal or of the same order as the dynamic/active power consumption itself. Multiple power domains, power-down regions within the chip, isolation cells between power domains, clock-gating, voltage step-down cells, body-bias and higher Vt transistors for the less performance-intensive circuitry are some of the potential solutions to handle the leakage problems in 90-nm SOC designs. However, implementing these techniques into designs requires among other things appropriate IP support (design blocks with accurate leakage characterization data), EDA tool support and tool flows to handle the additional design complexities (such as multiple power domains, power characterization, multiple-Vt library insertion), as well as an experienced team of physical design engineers who can work with all of the above.

Design for Manufacturability (DFM) for 90nm is more reality than hype. DFM refers to adjustments required (usually in) physical design of chips to account for unique process issues seen in DSM (deep sub-micron) process technologies. For example, designs need contextual RC extraction (to account for metal thickness variations due to Cu-CMP related dishing effects), contextual design rules checking (such as parallel run-length dependent width or spacing wire rules), or layout dependent transistor SPICE model fluctuations. With a supply voltage of 1.0V, the noise margins are significantly lower, causing power/ground voltage bounce and related signal integrity concerns.

Design IP providers play a critical role in the 90nm transition. Extensive characterization of the IP (through simulation and test-chips) to provide all the necessary power and speed data (e.g. state-dependent static leakage data for standard cells in a library) for usage by EDA tools is critical. Standard-cell and memory library support for different circuit architectures (multiple power domains) and process features (multi-Vt, multiple gate-oxide) will enable lower. There is a lot of good work coming out of the EDA industry to handle the various challenges outlined earlier. Smarter place-and-route tools, power optimizing synthesis tools (that use multi-Vt libraries), contextual RC extraction tools, static and dynamic IR drop analysis engines, and flexible physical verification strategies for complex topological design rules, are a few examples where the EDA industry has stepped up to provide solutions for the 90nm design challenges.

Business and Execution Challenges
While the larger IDM companies (such as Intel, TI) have had closely interacting process and design teams over the years and hence stand to benefit immensely going forward from this synergy, the smaller/medium-sized fabless companies are somewhat at a competitive disadvantage going forward. There has never been a greater need for fabless companies, pure-play foundries, EDA companies, and IP providers to work in close collaboration to overcome the 90nm barrier.

For the pure-play foundries that are pushing for the quick adoption of 90-nm technology, in addition to the high mask costs ($1 million for a set of 90-nm masks) for customers and the foundry customers’ inertia to change given an already troubled history with 130-nm, they are confronted with a customer base that by and large is unable to simply shrink down from the previous node because of all the design complexity issues discussed previously. Unless new business models enable fabless chip companies to successfully adopt 90-nm technology, the pure-play foundries are likely to run into financial rough weather in the next few years.

Future Trends and Business Opportunities
From the era of “Real Men Own Fabs” in the pre-1980s when IDM companies were the only ones playing, the establishment of pure-play foundries such as TSMC and UMC enabled the emergence of fabless semiconductor companies whose focus was purely on chip design, marketing, sales and management, leaving process technology development to outside experts. Back-end manufacturing activities like packaging assembly and testing were also outsourced to pure-play back-end companies such as ASE and AMKOR. The 1990s proved the tremendous success potential of the fabless model with several companies including Qualcomm, Broadcom, Xilinx and Cirrus Logic reaching the $1-Billion annual revenues landmark. For the fabless companies to continue to lead the product innovation curve however, a new business model has to emerge to enable them to surmount the 90nm design barriers.

One such business model is the emergence of specialized “design factories”, which will take architectural definition of chips from customers all the way to tape-out stage, handling all the front-end and back-end chip design activities. These design factories will occupy their rightful place in the fabless supply chain between the semiconductor companies (that will increasingly focus on chip definitions and system design to move up the value chain) and process foundries (which will innovate process technologies that will enable the future product technologies). Such “design factories” will comprise of experts with product areas domain expertise, experienced logic/physical designers who understand the DFM issues, and foundry engineers with experience in both process technologies and design flows.

This potential business model provides an excellent opportunity for India as a key player in this market. The outsourcing of chip design to their Indian design centers by established chip companies is not new, but this has triggered a process of developing a large pool of engineers with DSM design knowledge and experience base in India. The proximity to the pure-play foundries (in Taiwan and China) is another key advantage to establishing these design factories in India, given the increased inter-dependency required to execute on successful 90nm designs. In the software industry, India has emerged as a key geography not only for services but also for development, banking not just on cost competitiveness but also on quality. This success can be imitated in the semiconductor design space, where the 90nm transition provides a great opportunity for India-based companies to emerge as leading providers of design services, not based on cost but based on expertise, and to take a permanent place in the emerging supply chain model in the global semiconductor industry.

Shankar Pennathur is the director of technology and logistics for Centillium Communications Corp., a Fremont, CA-based supplier of communications chips. Pennathur can be reached at: shankar@Centillium.com