Tilera plans to unveil 100-core processors
By siliconindia   |   Tuesday, 27 October 2009, 20:32 IST
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San Jose: Network security firm Top Layer Networks is designing a network intrusion detection system using the 64-core processor from semiconductor startup Tilera, which has announced plans for a next-generation 100-core processor. The two firms are among a handful living at the edge of an emerging many-core era, reports EE Times. Analysts and researchers say it could take years and require major breakthroughs in parallel programming - before the broad computer and embedded industries can follow them. The transition to parallel software represents the hardest computer science problem in 50 years, said David Patterson, Professor of Computer Science at the University of California, Berkeley. Top Layer has an intrusion detection system that can scour packets at rates up to 4.4 Gbits/second using a set of ASICs and FPGAs that it created. Mike Paquette, Chief Strategy Officer at Top Layer said his team liked the fact Tilera taps existing Linux tools for symmetric multiprocessing systems, treating its many-core processor like a multi-CPU server. The approach lets Top Layer give a single core many jobs or spread a single job across many cores. "The hard part was converting our software from the ASIC and FPGA design, nothing specific to the Tilera software which was quite straightforward," said Paquette.