Aldec unveils RTL simulator with enhanced assertions

By siliconindia   |   Monday, 28 December 2009, 19:08 IST   |    1 Comments
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San Francisco: EDA vendor Aldec Corporation has unveiled its new Register Transfer Level (RTL) and gate level simulator for FPGA design and verification engineers. The company says that the Active-HDL 8.2 sp1 includes full support for Xilinx SecureIP, IEEE VHDL/Verilog-encrypted IP and an enhanced assertions bundle option. According to Aldec, IEEE 1800 SystemVerilog assertions (SVA), property description language (PSL) and Open Vera assertions (OVA) for legacy designs are the three assertion types that the latest assertion bundle supports. It also supports a dedicated assertions viewer, assertion debugging and complete visibility of assertions, properties and functional coverage statements through the simulator. Aldec said that the Active-HDL 8.2 sp1 is currently available for customers directly from the company and through its authorized global distribution chain.

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