Here Comes The 'Synopsys' New Designware Sensor And Control IP Subsystem
Designers can implement these sensor-specific DSP functions in hardware using a combination of native DSP instructions within the EM5D or EM7Dprocessor and tightly coupled hardware accelerators to boost performance efficiency and reduce power consumption by up to 85 percent compared to discrete solutions.
An optional IEEE 754-2008 compliant FPU reduces energy consumption by up to 10X for sensor applications requiring single- or double-precision floating point operations. Additionally, the ARC Processor Extension (APEX) technology enables designers to add their own user-defined instructions or existing hardware to the processor.
“Embedded sensor and control applications require a high level of integration with minimal power and area,” said John Koeter, vice president of marketing for IP and Prototyping at Synopsys. “The DesignWare Sensor and Control IP Subsystem gives designers a pre-integrated solution with flexibility and performance features so it can be optimized for each specific application. The subsystem’s combination of scalable performance, ultra-low power consumption and small silicon footprint enables designers to quickly integrate sensor and control functionality into their SoCs with less risk and effort.”
Availability
The new DesignWare Sensor and Control IP Subsystem is scheduled to be available in January 2015.
About DesignWare IP
Synopsys is a leading provider of high-quality, silicon-proven IP solutions for SoC designs. The broad DesignWare IP portfolio includes complete interface IP solutions consisting of controller, PHY and next-generation verification IP, analog IP, embedded memories, logic libraries, processor solutions and subsystems.
To accelerate prototyping, software development and integration of IP into SoCs, Synopsys’ IP Accelerated initiative offers IP prototyping kits, IP software development kits and customized IP subsystems for rapid integration of IP into SoCs.
Synopsys’ extensive investment in IP quality, comprehensive technical support and robust IP development methodology enables designers to reduce integration risk and accelerate time-to-market.
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