When multiple transistors were fabricated to execute a logical function in a physical space, the Integrated Circuit (ICs) came of age. Transistors joined together to perform logic functions like “and”, “or” and “not” are called “gates.” This combination of transistors, gates and their wire interconnects remains the basis of even the most complex chips today. LSI Logic, founded in 1981, was at the forefront of automating the design process for custom semiconductors and was among the first to introduce CMOS gate arrays as a highly integrated, low power solution for custom design. Indeed the innovations in custom design in the early 1980’s led to the coining of the term ASIC (Application Specific Integrated Circuit). Since then, the rush to stuff more and even more transistors on to ever-shrinking pieces of silicon has ruled the semiconductor industry dynamics. Density and clockspeed have dictated the growth curve till recently. The cost of stuffing millions of transistors, the IPs to run them, and the fabrication of these fine engines have put the chips in the billion-dollar bracket. However, the market is changing.

Custom solutions, which reduce time to market, offer reasonable functionalities, and are created with short design cycles have been an interesting development. Field Programmable Gate Arrays (FPGAs) has exploded, but lags way behind the ASICs. This has split the market down the middle. At one end, we have the high-performance, complex, high-cost ASICs. And then the FPGAs. Gartner/Dataquest expects only around 6% growth in the ASIC market this year but is projecting growth of over 10% for application-specific standard products (ASSPs) and over 14% for FPGAs and programmable logic devices. If you look behind the numbers and at the marketplace activity of late, it’s clear that a shift is under way. For cutting-edge IC designs, standard-cell and custom ASIC implementation is the ticket to the highest performance allowed by today’s silicon fabrication processes. But given that most IC designs don’t see huge unit volumes and most don’t require cutting-edge performance, designers often seek different solutions for standard-cell ASIC implementation.

Typical of any market dynamics, the industry is pushing both ends of the segment to a middle of advantages. In the late 1990’s System on a Chip (SoC) emerged as more than an interesting concept and became a mainstream approach for complex design. Re-use of pre-designed elements—commonly termed IP (Intellectual Property)—accelerated both the design and verification approach for complex design. This approach does not solve everything and as technologies approach the 90 nanometer level, further innovation is needed.

David Maliniak wrote in EE Times, “How you ultimately choose to implement your design is a matter of tradeoffs, of course, between expected unit volumes, performance requirements, and your market window. Once all of these are weighed, it may be that there’s a better way for you to go than with a standard-cell methodology.

Currently, digital logic can be implemented through four primary methods. FPGAs are the lowest in risk but carry the highest unit costs. Gate arrays are a middle ground that has fallen from wide use, as they call for only somewhat less custom mask making than standard cell. Standard cell is the option with the highest performance and lowest unit cost (good), but it also has the longest design cycle and highest NREs (bad).

Then there’s the fourth option. Quite a bit of excitement surrounds a reinvention of the gate-array concept that’s emerged in the past couple of years. Known variously as platform ASICs or structured ASICs, these devices offer performance levels that are just a process generation or so behind standard-cell performance, which is good enough for a very large number of applications.”

Echoing this sentiment is Sudhakar Sabada, vice president of Design Technology at LSI Logic. “The concept is still finding its feet and multiple opinions abound as to its key elements. However, the core of it is finding a consensus. A Platform ASIC will have some element or pre-definition, including some intellectual property. The customization of the platform can be executed rapidly and with low risk. The manufacturing cycle time and cost of prototyping will both be significantly reduced compared to cell based ASIC.” LSI Logic’s answer to the problem is its recently announced RapidChip Platform ASIC, semiconductor platform and design environment. The RapidChip solution is an approach to custom semiconductor design that combines advantages of both ASICs and FPGAs in a way that also minimizes or eliminates their disadvantages. The RapidChip solution incorporates CoreWare® from LSI Logic’s library of intellectual property, customisable high performance logic technology and a new methodology and tool set optimized to reduce design cost and cycle time.

Maliniak continues, “...It’s important to understand that structured ASIC cell logic blocks are complex cells. They typically include lookup tables, storage elements, multiplexers, inverting inputs, and cascading outputs, all common in FPGAs. A custom mapper that can directly map to individual complex cells yields the best quality of results.

Why should designers consider structured or platform ASICs for their chip implementation? Again, it’s a matter of tradeoffs. If you know that the ASIC you're designing will be produced in extremely large volumes, or if it needs a very large number of gates, or requires absolute best-in-class performance, then standard cell is probably the best way for you to implement it. But for mid-volume production runs, or for those without the budgets for standard-cell NREs, structured ASICs may be the answer.

Doug Bailey, Chip Express VP of Marketing, believes that structured ASIC can solve the problems related to non-recurring engineering charges and productivity. ASIC vendors have introduced platform-based, structured ASICs as a solution to the problems of non-recurring engineering (NRE) charges and productivity. Theoretically, the vendor performs the difficult work—purchase of intellectual property (IP), integration, and verification—enabling the designer to type a few thoughts into a DC shell, magically generating a custom ASIC implemented on a low-mask-count metal-programmable array based on the ASIC vendor's platform. However, the platform is tricky to define. In effect, the ASIC vendor must specify 90 percent of a customer’s chip. The chances of getting more than 50 percent right are slim. Moreover, the supplier must get everybody to use the same platform. In reality, platform-based ASIC designers are left with a chip that is 50 percent useful and is also in the hands of the competition. “We see designs coming in at multiple entry points,” says Steve Bateman, VP of engineering. An increasingly popular option is RTL handoff. “As we find ourselves with customers wanting to hand off at higher levels of abstraction, that gives us some interesting challenges from the design-flow perspective,” he adds.

While structured ASICs are the right choice for many designers, plenty of other designers ply the waters of FPGA design. This can be as a prototyping vehicle or for small-to-medium production runs. The fact is that FPGAs are becoming more affordable while performance continues to rise. Though large FPGA vendors continue to provide tools for their devices, others are stepping into the fray with everything from standalone tools to entire flows, writes Maliniak. As FPGAs continue along the complexity curve, tool flows for FPGAs are beginning to resemble, in certain respects, traditional ASIC flows. This can be seen with technologies such as physical synthesis and formal verification moving into the FPGA flow.
“Cost-out-of-door and time-to-market are becoming increasingly important, and the entire industry is gearing to help shorten this,” observes Sabada at LSI Logic. “EDA, fab tools, verification tools—all are now blurring lines and beginning to work together, as first-time right becomes the critical factor for a company’s survival.”

“Structured ASICs are low, broad platforms that make good business and technical sense to most designers. They don’t enact the dream of 90 percent preverified technology delivered just as the customer required. But they deliver a solid base for starting a design with low up-front NRE and low implementation risk,” says Bailey. “The ASIC business is caught between a rock and a hard place: expensive unit prices for FPGAs on one side and unreachable mask costs on the other. The new structured ASICs with high-performance, reasonable I/O flexibility and a ton of memory will help the endangered ASIC species to survive and thrive.”