Finally here is a man who can truly claim to practise what he preaches. Google on “Naveed Sherwani” and it returns about 5510 hits (in less than a proudly-claimed 0.10 seconds). The first 10 links showcase the learned professor’s authorship, “Algorithms for VLSI Physical Design Automation,” now into its third edition and a textbook at engineering colleges around the world. Many of Sherwani’s students work at some of the leading design centres around the country, and Sherwani himself has moved on from academia to real world. The best part, though, is he now practises what he preaches—and the venture world believes him. “When I wrote the book twenty years ago, I learnt some interesting things about the silicon business,” says Sherwani. His contention was that the biggest challenge in getting a chip out of the door lies in the fluidity of the design process and methodology. “This is not a people-centric industry—you cannot build a billion-dollar chip company with a great team alone, even if the team is the best of talent. And this is not a tools-dependent industry—how many tools of the eighties exist now? What is then left is the big slack in the methodology from design to tape-out. All we have done is picked up this slack and opened up visibility to the process,” says Sherwani, furiously sketching out his model blocks on the board.

Post the academic stint, Sherwani spent an extended period in methodology research at Intel Microprocessors, and zeroed in on three key ASIC industry parameters—cost, predictability (making it out of the door in predicted time), and reliability (working first time onwards). With a reference design costed for manufacturing at TSMC and packaged at ASE, Sherwani went out into the market and sourced quotes from IBM, LSI Logic, NEC, Toshiba and some other players. The cost for each vendor varied wildly, intriguing the academic. Further enquiries elicited more visibility into the costing process, the design methods, and the strategy for profitability. “The non-recurring engineering (NRE) cost for one design that would finally reach silicon was paying for the cost of design of four others that would never reach silicon,” says Sherwani. “It wasn’t the ideal amortization process, and this creates a barrier to entry that only rises every year.” There was an “a-ha!” in there, but the team said, “Well, now what?” recalls the CEO, who then spent the next two years in devising the OpenModel—a supply chain visibility and business process control map—at the chip giant, validating the model over 28 successful tape-outs.

Traditional ASIC use design tools that is another fixed cost, and the tools are used to only about a quarter of their full feature abilities. “Companies were buying shelfware, and also using them for only an eight-hour shift, whereas the true benefits of the tools would accrue only from using them for more than an eight-hour window,” he declares. As another first, he established a team in India that followed the sun, and drove down the cost of ownership for tools at the chip company.

After much diligence in the OpenModel, Sherwani found Intel Microelectronics shying away from a more robust adoption of the strategy, and moved on to found Open Silicon in 2003. “I realized that the ASIC industry should have been a commodity business for any real growth, and such a commoditization can happen only when the entire process within the business is open for any entrant,” confides Sherwani. The high costs, he says, is in part due to the perception of the business dynamics: ASIC sales are opportunity driven, rather than capability driven, whereas the costing process is in direct contrast. Contenders like IBM were more interested in pushing the envelope of ASIC design, and thus were involved in the higher-end of the design ladder. Others were fab vendors, and thus more concerned about filling up capacities. Since cost of the fab was intrinsically tied to cost of design, the x-factor in costing went up.

And then there is the manufacturing visibility that affects the predictability and reliability of the chip. When ASIC fab vendors take on projects, customer-driven changes in specifications and methodologies throw the delivery commitments out of realistic possibilities, and the clients end up with delayed products that cost much higher, and do not measure up well in the reliability charts. The fluidity in the process was not a very visible entity in the decision-making process, and clients realized the impact only when targets were missed.

Standing the ASIC costing and manufacturing methodologies on its head, Sherwani is insisting that Open Silicon’s model will make the difference. Where traditional ASIC providers hold 2.5x as a baseline chip cost, Sherwani is slicing the number to less than half that, while pulling up predictability from the dismal 20 percent to well over 90 percent, and promising first pass reliability that hovers around the same figure. “Fixing the methodology is the secret sauce,” he says.

At Open Silicon, Sherwani is staying away from the “science” projects—high end design projects that tempt the sales teams. “We require our engineering teams to check off the project scope against our rigorous list, and we accept only those that match up,” he says. The second platform he is attacking is client visibility and participation levels in the entire process. “We found in our research that once you stabilize the flow, 90 percent of the delays are caused by the customer,”Sherwani says. “By including the customer decisions and sign-offs in the project tracking, we let the customer decide explicitly whether a change in requirements is worth the impact on cost and schedule—and we find that a customer who is fully aware of the state of progress often will decide that a change just isn’t worth it.”

In another move contrary to the industry norms, Sherwani is building teams with surgical precision. “In my research, I found that a team consisted of people with broad skill sets—a designer who worked on timing in one project would be working on DFT in another, and then on analysis in the third,” discloses the CEO. “At Open Silicon, we have project managers who will possess a broad skill set, but the rest of his or her team will consist of people with deep experience in specific areas. That builds up our speed-of-response, and the client is free to talk to any of our team members.” And then again, Sherwani is careful about selecting IP that has been proved in silicon. “As I repeat often, we do not restrict clients from making their choices—our goal is help them understand the reality of the process, and help them evaluate their goals in light of these realities, and the level of risks they are willing to accept.”

True to the company name, Sherwani insists that his clients evaluate all tools and fab vendors available and make their choices. “We are impartial to any of these, and will gladly work with any and every one of the suppliers in the market.” With a healthy pipeline of projects in hand, Sherwani is proving that ASIC can really contend against platform design on cost and performance. “We are even executing drop-ship for certain clients, and that has made us a true, open supply chain enabler for the ASIC industry. Even though we insist on fixed methodologies, tools, and proven IP, Open Silicon has delivered complex design to the market—well under the price of a platform chip,” says Sherwani. With a resounding vote of confidence from the investing team, the academic-turned-entrepreneur is influencing a change in the market dynamics. “Sherwani’s team may end up breathing new life into ASICs,” says Erach Desai, analyst with American Technology Research. Well said.