Today’s IC designers have a tough job at hand. As the race continues to add exponentially more transistors on a chip and uphold the ‘Moore’s law’, complexities in IC design are rising rapidly. Some of these challenges and the contributions made by the EDA companies and their possible future contributions are discussed here.

Today’s IC Design Challenges
As the process nodes shrink, ecosystem players face three key challenges: manufacturability, complexity, and scale.

To successfully get nanometer-scale designs to market, semiconductor companies must address a growing array of challenges—from ever-more stringent design rules to increasing chip layout complexity. Designers must also contend with the physical effects that become much more troublesome at these micro geometries. Lithographical and CMP manufacturing effects can have significant impact on both functional and parametric yields. Process variations across the die, wafer, and batch affect the yield, performance, and reliability.

Complexity and scale of chip design are attributed to the complications of combining lots of diverse functionalities onto a single chip, plus the computational burden of creating, managing, and analyzing the vast amounts of data needed to capture the design. Design complexity and size continually escalate disregard of the process node used. The International Technology Roadmap for Semiconductors (ITRS) 2006 update predicts that the amount of digital logic on a typical consumer product ASIC (Application Specific Integrated Circuit) will double every three years through 2020. The capacity and speed enhancements are required to handle large designs on the newest process nodes. Also there is a need to improve team productivity and project predictability for large complex chips on any node.

As the industry moves towards smaller process geometries, the integration of digital and analog, and mixed-signal circuits makes predictability in a design flow increasingly difficult. Higher levels of integration and rapid adoption of system-on-chip (SoC) and system-in-package (SiP) form factors create new signal-integrity challenges. Added to this, if you consider shrinking product lifecycles and time-to-market pressures, IC design can be as complex as building an aircraft!