Today's IC Design Challenges and Solutions from the EDA Industry Date:   Wednesday , January 02, 2008 Today’s IC designers have a tough job at hand. As the race continues to add exponentially more transistors on a chip and uphold the ‘Moore’s law’, complexities in IC design are rising rapidly. Some of these challenges and the contributions made by the EDA companies and their possible future contributions are discussed here. Today’s IC Design Challenges As the process nodes shrink, ecosystem players face three key challenges: manufacturability, complexity, and scale. To successfully get nanometer-scale designs to market, semiconductor companies must address a growing array of challenges—from ever-more stringent design rules to increasing chip layout complexity. Designers must also contend with the physical effects that become much more troublesome at these micro geometries. Lithographical and CMP manufacturing effects can have significant impact on both functional and parametric yields. Process variations across the die, wafer, and batch affect the yield, performance, and reliability. Complexity and scale of chip design are attributed to the complications of combining lots of diverse functionalities onto a single chip, plus the computational burden of creating, managing, and analyzing the vast amounts of data needed to capture the design. Design complexity and size continually escalate disregard of the process node used. The International Technology Roadmap for Semiconductors (ITRS) 2006 update predicts that the amount of digital logic on a typical consumer product ASIC (Application Specific Integrated Circuit) will double every three years through 2020. The capacity and speed enhancements are required to handle large designs on the newest process nodes. Also there is a need to improve team productivity and project predictability for large complex chips on any node. As the industry moves towards smaller process geometries, the integration of digital and analog, and mixed-signal circuits makes predictability in a design flow increasingly difficult. Higher levels of integration and rapid adoption of system-on-chip (SoC) and system-in-package (SiP) form factors create new signal-integrity challenges. Added to this, if you consider shrinking product lifecycles and time-to-market pressures, IC design can be as complex as building an aircraft! Power management is another challenge faced by companies across the design chain. Power considerations in portable and wireless consumer devices have become a key part of product specifications. Even for wired devices and other industry segments in which battery power has not traditionally been an issue, considerations of packaging, reliability, and cooling costs bring power consumption firmly to the forefront at smaller geometries. In particular, as designs migrate to sub-90nm process nodes, power management becomes a serious concern across the entire design and manufacturing chain. There is a clear need for power-aware infrastructure that will benefit design teams; ASIC, library, IP, and tool vendors; equipment providers; and manufacturing facilities alike. EDA: Need for a Holistic Approach for Addressing Design Challenges In the early days of the EDA industry, companies focused on technology or products, offering point tools that automated some aspects of the design chain. The players largely focused only on enhancing the features in their product instead of looking at industry needs holistically. As a result, the products were not necessarily aligned with customer needs, and that left the designers with the more complex task of integration and design optimization. In a less disaggregated environment, where design teams were smaller and IC design less complex, this did not pose a huge problem. EDA companies can no longer address various aspects of the design chain in isolation. They need to move towards a customer centric approach, look at the design chain in its entirety, and develop solutions that optimize and not just integrate various design elements. Clearly, a holistic approach is the way forward. EDA companies must truly partner with their customers, and indeed with the ecosystem players, to help work through their challenges, reduce design risk, and shorten time-to-productivity. Manufacturability challenges become diverse and widespread at 65nm and below, and driving true design for manufacturability (DFM) integration into early stages of the design flow is becoming imperative in order to reduce risk. The Low Power Challenge – Power Forward Initiative As mentioned earlier, power is a critical issue in electronic design. In the recent past, isolated efforts to lower power consumption have been made. To achieve the required power targets, design teams are increasingly adopting advanced power management techniques such as multi-supply voltage (MSV) and power shut-off (PSO). Such techniques, however, increase design complexity and introduce risk. Conventional design flows fail to address the additional considerations for incorporating advanced low-power techniques. Consequently, design teams often resort to methodologies that are ad hoc or highly inflexible. The results are lower productivity, longer time to market, increased risk of silicon failure, and inferior tradeoff among performance, timing, and power. As the industry pushes toward smaller process geometries, the existing design infrastructure must be upgraded holistically to automate power-lowering design techniques. Most power-control methods in use today are manual and implemented ad hoc, leading to increased risk and cost. Across the design and manufacturing chain, an urgent need has emerged for an automated power-aware design infrastructure. Power Forward Initiative (PFI) is one such initiative to facilitate and support a new era of low-power design innovation. PFI has gained tremendous momentum with over 20 leading electronics companies joining the Initiative, including Freescale Semiconductor, UMC, TSMC, AMD, Applied Materials, NEC, and ARM. The Benefits of Open Standards Open standards provide the companies within the ecosystem with an opportunity to integrate innovative design methodologies, addressing some of the most complex industry concerns existing today. The OpenAccess Coalition, an organization that comprises of world leaders in IC design, is responsible for OpenAccess, a community-driven initiative that provides an interoperability platform for complex IC design based on a common, open, and extensible architecture, within the industry as more companies deploy the technology within their design flows, or roll out OpenAccess-supported applications. Open standards will also be critical in the future. Existing initiatives include the Open Verification Methodology (OVM) which is the first truly open, interoperable, and proven verification methodology. The OVM is an open-source SystemVerilog class library and methodology that defines a framework for reusable verification IP (VIP) and tests. It includes guidelines for using the class library and is scalable to system level verification. OVM has open source IEEE 1800 class library, runs on any compliant simulator, provides building blocks (objects), and a common set of verification related utilities. In conclusion, the EDA industry continues to play a crucial role in providing solutions to the semiconductor industry – it is the glue that holds the industry together. EDA companies must leverage their broad knowledge of technology offerings; work closely with the ecosystem players to offer comprehensive market-specific solutions that directly address their customer’s most pressing problem: how to shrink time-to-market while packing in more functionality into a smaller area. The author is Marketing Director, Cadence Design Systems. He can be reached at communications_india@cadence.com