Magazine : Deepali Gangwar
Current
ASIC DESIGN INTERN
Education
M.Tech vlsi design
Industry
Semiconductors/Electronics
Deepali Gangwar ’s experience
Design Cum TESTING ENGINEER
at
MTE
, Pune, INDIA
April 2008 – May 2009
Industry: Semiconductors/Electronics
Functional area: IT Sw- Embedded / EDA / VLSI / ASIC / Chip Design
design boards using FPGA to interfce with other devices and
write testcode for them in VHDL language.
write testcode for them in VHDL language.
Deepali Gangwar ’s education
M.Tech [vlsi design],
Mody Institute Of Technology And Science, Lakshmangarh, Rajasthan [Currently,Studying]
, Jaipur, INDIA
PG Diploma [VLSI DESIGN],
Pune University, Pune , Maharashtra. [February,2008] , Pune, INDIA
B.tech [ECE],
m.j.p.rohilkhand university [May,2007] , Bareilly, INDIA
Deepali Gangwar ’s additional information
Interests:
VLSI , New Technologies, Books
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