Senior Project Engineer
at
Wipro Technologies
, Chennai, INDIA
August 2007 – Currently Working
Industry: Semiconductors/Electronics
Functional area: Mixed Signal Validation
Work in mixed signal validation. Done projects for clients like
Intel, Actel, Wipro New Logic.
validation flows known are
Ultrasim, XA pre silicon validation flows such as ERC (Electrical
rule check, SRC (Schematic Rule check), FV (Formal Verification),
Verilog In (Schematic generation from synthesized verilog code),
Extraction.
Worked on validation tools such as Hspice, Spectre,
XA, Ultrasim, Finesim, Hsim etc.,
Validation done for projects
like Crystal Oscillator, PXP, DDR blocks.