Magazine : Manish Sarda
Current
Working
Education
B.Tech/B.E. Electronics & Communication
Industry
Semiconductors/Electronics
About Manish Sarda
Working in Analog & Mixed signal validation for more than 2.5 years. Like to work dedicately to meet the customer requirements and maintain the quality of deliverables is the first moto.
Manish Sarda ’s experience
Senior Project Engineer
at
Wipro Technologies
, Chennai, INDIA
August 2007 – Currently Working
Industry: Semiconductors/Electronics
Functional area: Mixed Signal Validation
Work in mixed signal validation. Done projects for clients like
Intel, Actel, Wipro New Logic. validation flows known are
Ultrasim, XA pre silicon validation flows such as ERC (Electrical
rule check, SRC (Schematic Rule check), FV (Formal Verification),
Verilog In (Schematic generation from synthesized verilog code),
Extraction. Worked on validation tools such as Hspice, Spectre,
XA, Ultrasim, Finesim, Hsim etc., Validation done for projects
like Crystal Oscillator, PXP, DDR blocks.
Intel, Actel, Wipro New Logic. validation flows known are
Ultrasim, XA pre silicon validation flows such as ERC (Electrical
rule check, SRC (Schematic Rule check), FV (Formal Verification),
Verilog In (Schematic generation from synthesized verilog code),
Extraction. Worked on validation tools such as Hspice, Spectre,
XA, Ultrasim, Finesim, Hsim etc., Validation done for projects
like Crystal Oscillator, PXP, DDR blocks.
Manish Sarda ’s education
B.Tech/B.E. [Electronics & Communication],
Velammal Engineering College, Chennai, Tamil Nadu. [May,2007]
, Chennai, INDIA
B.E [E.C.E],
VEC [Currently,Studying]
Manish Sarda ’s additional information
Interests:
Like to work in different flows and explore knowledge from all sides.
Taking responsibility of the work allocated.
Like to regularly exercise, play snooker.
Awards and achievements:
White paper on finding power for u-partition blocks from XA.
Apperciation from Client on execellent deliverables.
Raising Issues/Bugs at the right time.
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