Magazine : Ranganath Narayan
Current
Sr.design Engineer
Education
B.E Inst.Tech
Ranganath Narayan ’s experience
Sr.Design Engineer
at
ST Microelectronics
, Greater Noida
Working/Currently
Testing & Characterization of Analog and Mixed Signal IP’s in
TR&D group. Major Roles and Responsibilities :
Worked on the Silicon validation of 45nm, 65nm, 90nm
advanced CMOS IO buffers such as LVDS, SRC, DDR2, DDRSDRAM,
I2C, CFLED, PCI, OSC, IMG ,Compensation blocks, Up
gradation of IO Measurement System : Reduction in the test cycle
by Automation, integration and synchronization of various
measurement and generating instruments, Development and
upgradation of various Static and Transient parameter
measurement software using LabVIEW. . System Configuration
for Automating measurement setup for IO measurement system
using NI DAQ. The Lab VIEW VI “ IO_Validator “developed to
perform all the measurement sequentially, automatically
generating the report and without manual intervention. All the
measurement parameter VI’s brought into single platform.
TR&D group. Major Roles and Responsibilities :
Worked on the Silicon validation of 45nm, 65nm, 90nm
advanced CMOS IO buffers such as LVDS, SRC, DDR2, DDRSDRAM,
I2C, CFLED, PCI, OSC, IMG ,Compensation blocks, Up
gradation of IO Measurement System : Reduction in the test cycle
by Automation, integration and synchronization of various
measurement and generating instruments, Development and
upgradation of various Static and Transient parameter
measurement software using LabVIEW. . System Configuration
for Automating measurement setup for IO measurement system
using NI DAQ. The Lab VIEW VI “ IO_Validator “developed to
perform all the measurement sequentially, automatically
generating the report and without manual intervention. All the
measurement parameter VI’s brought into single platform.
Ranganath Narayan ’s education
B.E [Inst.Tech],
SJCE - Mysore [2004/July]
, Mysore
Ranganath Narayan ’s additional information
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