Magazine : Bharti Dadhich
Current
Electronics Engineer
Education
M.Tech Microelectronics
Industry
IT-Hardware and Networking
About Bharti Dadhich
M.Tech from BITS,Pilani in Microelectronics. Currently working with Freescale Semiconductors,Noida as Design Engineer.
Bharti Dadhich ’s experience
Trainee
at
Hewlett Packard(HP)
, Bangalore, INDIA
January 2009 – June 2009
Industry: IT-Hardware and Networking
Functional area: IT Sw- Embedded / EDA / VLSI / ASIC / Chip Design
Design Engineer at Freescale Semiconductor , Noida, INDIA
June 2010 – December 2010
Industry: IT-Hardware and Networking
Functional area: Engineering Design / R and D
Working as a Design Engineer.
Tools: Cadence Suite for IC Design
(Virtuoso Layout Editor CDBA and OA, Schematic Chip Assembly
Router), Mentor Caliber DRC, DFM & LVS Key Responsibilities:
Testcase Generation & Validation of P-CELLS. Layout extractions,
DRC, DFM rule checks and LVS for CMOS55fg, TSMC18.QA-Cells
Validation. Pcells: DRC, DFM, LVS Parameters, connectivity models
OA, abutment, stretch handles, Callbacks.Simulation
(Virtuoso Layout Editor CDBA and OA, Schematic Chip Assembly
Router), Mentor Caliber DRC, DFM & LVS Key Responsibilities:
Testcase Generation & Validation of P-CELLS. Layout extractions,
DRC, DFM rule checks and LVS for CMOS55fg, TSMC18.QA-Cells
Validation. Pcells: DRC, DFM, LVS Parameters, connectivity models
OA, abutment, stretch handles, Callbacks.Simulation
Bharti Dadhich ’s education
M.Tech [Microelectronics],
Birla Institute of Technology & Science (BITS), Pilani [June,2009]
, Jaipur, INDIA
Bharti Dadhich ’s additional information
Interests:
New Technology
Awards and achievements:
• Awarded 3rd Prize in “Manthan -2003”, a state level paper presentation in technical symposium held on 8th March 2003 at Poornima College of Engineering & Technology, Jaipur.
Participation in Paper Presentation in 6th National Convention of ISTE Student chapter held at J.N.T.U, Hyderabad
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