Magazine : Siddesh H Banakar
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Stud RV VLSI Banglore
About Siddesh H Banakar
INVERTER SIMULATION AND LAYOUT IN 180NM TECHNOLOGY:
Simulated for different loads in the 180 nm technology Layout of Inverter was drawn and physical verification was performed. We learnt delay is a function of Load, supply voltage and transition. Understood the nuances of custom layout design and the usage of different layers while drawing the layout.
• STUDY OF 180NM TECHNOLOGY FOUNDRY DOCUMENT:
Studied and prepared a report on the devices supported, Layers usage and understand the terminology used in the document. Understood the key rules to focus on for custom layout design.
• PHYSICAL DESIGN AND IMPLEMENTATION RISC PROCESSOR
The project was aimed at Physical Design and Implementation of RISC Processor. The design incorporated 13 macros (2 PLL’s,1clk multiplier and 10 memories) , 22000 cell instances and 8 clocks (3 propagated and 5 generated clock).The project mainly focused on floorplanning , placement ,CTS (clock tree synthesis)and routing ,DRC and LVS
PERL SCRIPTING
To calculate number module from verilog netlist
To calculate total capacitance , resistance values with their units from spef file
To find whether the code is Verilog or VHDL
Final Year Project:
DESIGN AND SIMULATION OF DDR2SDRAM CONTROLLER USING VERILOG
DOUBLE DATA RATE memory is the latest in high-performance memory module. In SDRAM, only one of the clock wave edges is used, but DDR2 SDRAM references both, effectively doubling the rate of data transmission. DDR2 memory provides boost in performance compared to regular SDRAM. The core accepts commands using a simple local interface and translates them to the command sequences required by DDR2 SDRAM devices. The core also performs all initialization and refresh functions. This technology of the future supports peak bandwidths in traditional 64-bit module.
Specialties
Linux, VI ,Perl,TCL,CUSTOM flow (circuit design to GDSII),ASIC flow (RTL to GDSII)
Simulated for different loads in the 180 nm technology Layout of Inverter was drawn and physical verification was performed. We learnt delay is a function of Load, supply voltage and transition. Understood the nuances of custom layout design and the usage of different layers while drawing the layout.
• STUDY OF 180NM TECHNOLOGY FOUNDRY DOCUMENT:
Studied and prepared a report on the devices supported, Layers usage and understand the terminology used in the document. Understood the key rules to focus on for custom layout design.
• PHYSICAL DESIGN AND IMPLEMENTATION RISC PROCESSOR
The project was aimed at Physical Design and Implementation of RISC Processor. The design incorporated 13 macros (2 PLL’s,1clk multiplier and 10 memories) , 22000 cell instances and 8 clocks (3 propagated and 5 generated clock).The project mainly focused on floorplanning , placement ,CTS (clock tree synthesis)and routing ,DRC and LVS
PERL SCRIPTING
To calculate number module from verilog netlist
To calculate total capacitance , resistance values with their units from spef file
To find whether the code is Verilog or VHDL
Final Year Project:
DESIGN AND SIMULATION OF DDR2SDRAM CONTROLLER USING VERILOG
DOUBLE DATA RATE memory is the latest in high-performance memory module. In SDRAM, only one of the clock wave edges is used, but DDR2 SDRAM references both, effectively doubling the rate of data transmission. DDR2 memory provides boost in performance compared to regular SDRAM. The core accepts commands using a simple local interface and translates them to the command sequences required by DDR2 SDRAM devices. The core also performs all initialization and refresh functions. This technology of the future supports peak bandwidths in traditional 64-bit module.
Specialties
Linux, VI ,Perl,TCL,CUSTOM flow (circuit design to GDSII),ASIC flow (RTL to GDSII)
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