It’s no secret that the best way to reduce complexity has been to modularize and bring about higher levels of abstraction. This process stratifies the products and services in the industry and allows innovators to operate at higher levels of abstraction, reducing complexity, and thereby setting the stage for breakthroughs at every level.

Exemplarily, we now feature novel approaches by entrepreneurs who are striving to provide tools and solutions that overcome the major challenge to design flexibility in the semiconductor industry. The need of the hour is to reduce integrated chip (IC) design complexity by adopting a higher level of abstraction. What separates the winners from the runners up in the highly competitive world of semiconductors is the ‘time to market’ factor. And the one primary force that decides this key parameter is how the design complexities are addressed. Taking this task forward is Atrenta Inc, an early design closure company. It was started to realize the need among its customers to move the design analysis and optimization up from the gate level to the Register Transfer Language (RTL) level. “Fixing problems early has many benefits. One important benefit is that the iteration loop is cut short early in the process, so fixing problems at that stage is easier and quicker. To accomplish this goal the company has developed products that can essentially “predict” what will happen to a design as it moves into implementation. This ability to perform early analysis and optimization is the foundation of Atrenta’s innovation,” says Mike Gianfagna Vice President – Marketing. On the question of evolving trends in IC design, “complexity management” is cited as the term that sums up the scenario and higher levels of abstraction as the key to the solution. Further, the need to re-use IP is found to be critical, as well as recycling of architectures in the form of platform-based design.

Breaking Traditional Models

Traditions implicitly bring about inflexibility, which in a changing world results in escalated costs. This inflexibility in the ASIC market had a stifling effect, which proved to be the opportunity for Open-Silicon Inc. It has set about challenging the traditional supply chain for ASIC chip development. “Our strength lies in the Open model, whereby our clients are given a host of choices,” says Dr. Satya Gupta, VP Engineering. The chip supply chain optimization is achieved through providing and advising on a wide portfolio of fabrication process technologies, pre-qualified IP, package assembly and test solutions.

Also the company differentiates itself from being just another design service provider by taking charge of a larger section of the product design life-cycle. By doing so, it has also tapped into a larger portion of the revenue sources.