Lattice Launches its Fourth Generation ECP4 FPGAs
Bangalore: Lattice Semiconductor has considerably increased the performance with its next generation LatticeECP4 FPGA family, with low cost, low power mid-range FPGA (field-programmable gate array) market.
The next generation Lattice ECP4 features a 6 Gbps Serializer/Deserializer (SERDES) in low cost wire-bond packages, powerful digital signal processing (DSP) blocks and hard IP-based communication engines for cost and power sensitive wireless, wire line, video and computing markets.
The ECP4 also features lower power architecture. It is optimized for mid-density devices, and not based on high-density high overhead platform. Modified logic routing power ratio helps achieve higher performance with modest dynamic power increase. It also features higher bandwidth and performance.
This device is ideal for developing mainstream platform for a variety of applications such as remote wireless radio heads, distributed antenna systems, cellular base stations, Ethernet aggregation, switching, routing, industrial networking, video signal processing, video transmission and data center computing.
The LatticeECP4 FPGAs contain up to 16 CEI-Compliant 6 Gbps SERDES channels with embedded physical coding sub-layer (PCS) blocks in both low cost wire-bonded and high performance flip chip packages, giving customers the choice to deploy the LatticeECP4 FPGA in chip to chip as well as long reach backplane applications.
It also features powerful DSP blocks with 18x18 multipliers, wide ALUs, adder-trees and carry chains for cascade ability. The flexibility of 18x18 multipliers can be split into 9x9 or it can combine into 36x36 to perfectly match customers’ applications requirements. Moreover, up to 576 multipliers can be cascaded together to build complex filters for wireless remote radio heads (RRH), multiple-input and multiple-output (MIMO) based radio frequency antenna solutions and video processing applications.
The Lattice ECP4 is up to 50 percent faster than its previous device and it features 1066 Mbps DDR3 memory interfaces and 1.25 Gbps LVDS (low-voltage differential signaling) input and outputs that are also capable of being provisioned as serial gigabit Ethernet interfaces. It also has 66 percent more logic resource and 42 percent more embedded memory to empower design engineers to constructs complete systems on chip in FPGAs.
Lattice has been a pioneer in providing cutting edge innovations in economical devices for customers. Providing the Lattice Diamond 1.4 beta software, customers can design with ECP4. Some selected customers are already designing using this software which is the new flagship design environment for Lattice FPGA products and provides a complete set of powerful tolls, efficient design flow and a UI that enables designer to more quickly target sensitive FPGA applications.
Device samples will be available in the first half of 2012 and high-volume production delivery is scheduled for the second half of 2012.
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