December - 2012 - issue > In Conversation
Mantra to drive New Generation of Semiconductors
Nimish Modi
Senior Vice President, R&D-System and Software Realization Group, Cadence Design Syste
Friday, November 30, 2012
Headquartered in San Jose, CA, Cadence Design Systems, Inc. (NASDAQ: CDNS), is an electronic design automation software and engineering services company founded in 1988 by the merger of SDA Systems and ECDA, Inc.

Success is making Customers successful

As a technology leader, we constantly push the innovation envelope to help solve the next generation of technology challenges. We are extremely customer driven and develop comprehensive end-to-end solutions that are built on strong foundational technologies and close collaboration with customers and industry partners. Our customers’ challenges are at the core of virtually every decision we make, and we firmly believe that we can succeed only by making our customers successful. We also believe in collaboration for success – forging strong relationships with leading ecosystem companies such as IP providers and foundries.

Major paradigm shift EDA sector is witnessing

"Smaller, faster, cheaper" has always been the mantra driving a new generation of computer chips and EDA has played a key role in enabling this to happen. In an increasingly applications-driven, highly mobile, and hyper-connected electronics world, unique demands are put on semiconductor and system providers. Not only does EDA need to provide solutions to facilitate the development of low-power, mixed-signal chips at ever-smaller process nodes, but it now needs to understand the software component as well and provide comprehensive hardware-software system-level convergence solutions.

Additionally, time-to-market and cost pressures are driving hardware and software IP reuse, which in turn calls for the creation of a sophisticated infrastructure for IP creation, sourcing, integration, and management. This highly complex set of interdependent variables requires a very tight, integrated network of EDA companies, ecosystem partners and leading-edge customers, to collaborate and co-develop solutions. This sea change in the market requirements and resulting customer needs poses an interesting challenge but is an opportunity for the EDA community to evolve beyond its traditional space and become a broader system-level hardware and software solution provider.

Trends shaping the industry

Despite the escalating complexity of hardware, software is fast becoming the primary element of system differentiation. Software applications determine the user experience, and while this may be most obvious in the consumer space, other vertical domains such as communications infrastructure, medical electronics, and automotive are also adopting this new paradigm. As a consequence, semiconductor vendors are now being required by their original equipment manufacturer (OEM) customers to provide various levels of software along with the SoC. This has created the need for these traditional hardware providers to build up a software competency in their organizations. Today there is a need to decouple software development from silicon availability, and there are hardware abstraction platforms that make it possible to develop software early in the process. Many system companies are now moving toward a vertical integration model to develop the hardware and software components themselves, which are customized to meet their specific needs and tightly integrated to deliver an optimized end product.

Systems and semiconductor companies now are required to provide not only silicon, but complete hardware-software systems ready for applications or “apps” deployment. To enable this, we offer an open, connected, and scalable solution – the Cadence System Development Suite – that includes four connected platforms to allow concurrent hardware-software development.

Evolving set of Customer Challenges

Mobility, video, and cloud computing are the key growth drivers for our customers in the electronics industry, and these areas constantly drive requirements for advanced computing, communications, and storage technology.

Moore’s law, an observation over the history of computing hardware, states that the semiconductor industry doubles chip density approximately every two years. This has resulted in increasing functionality being packed onto individual chips. Today multicore computing platforms are everywhere, and the push for smaller form factors, more functionality, and better energy efficiency continue to drive the trend towards smaller transistor geometries and advanced process nodes. System-on-Chip (SoC) development costs have exponentially increased and are now estimated to be up to $100 million for a new advanced-node SoC design. Chip companies must be able to sell a significant volume of chips to recoup that investment, and that is done primarily through multiple derivative designs for different applications.

As an EDA company, we address the need to integrate analog, digital, and mixed-signal logic on SoCs, which has given rise to new design and verification challenges. Semiconductor providers are increasingly driving “horizontal integration” to accommodate smaller form factors, lower cost and higher performance.

Increasing functional complexity cannot be adequately addressed through traditional design and verification techniques. What is needed is a higher level of abstraction in the form of transaction level modeling (TLM). Today high-level synthesis tools can factor in user-supplied constraints and automatically generate Register Transfer Level (RTL). Advantages on the verification front are just as important, either through the productivity benefits of using a high-level test bench or by enabling the critical verification phase to begin earlier in the design process.

Looking beyond the chip, challenges for package and printed circuit board (PCB) designers have also significantly increased. The movement to advanced nodes contributes to significant signal and power integrity and thermal challenges for board designers. Higher I/O counts and multiple stacked die create additional challenges for package design. All of these demand higher accuracy and higher performance analysis solutions and drive the need for the integrated, system-level flow for design, verification, and analysis that Cadence provides.

Power packed role of Low Power

Power is a critical "care about" for consumers and system providers alike, since it is key to the system form factor, cost, and performance, as well as the user experience. Low power in absolute terms is important, as is power efficiency, which is measured in performance per watt per cubic foot. Add to this a typical data center’s appetite for primary power and cooling, and it’s apparent that power is an extremely important element of their Total Cost of Ownership (TCO). It’s imperative that a holistic, system-level approach to designing for power is taken – one that comprehends the architecture, implementation, and physics of the device. While advanced power management techniques can be implemented at the chip level, an often-overlooked aspect is the need to ensure that the software stack is also designed to take advantage of those sophisticated features.
(As told to Anamika Sahu)

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