Leads a team of elite, seasoned Verification professionals
focused on next generation verification automation and productivity techniques. She
has been providing consultancy to leading edge semiconductor houses on various
verification challenges for nearly a decade.
Ben is currently an HDL and Property languages (PSL,
SVA)trainer and consultant and also a member of the VHDL and Verilog Synthesis
Interoperability Working Group of the Design Automation Standards Committees, and
Accellera OVL and PSL and SVA standardization working groups. . He also
authored more than 5 Books.