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Xilinx picks 28nm process for next-generation FPGAs
By siliconindia
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Tuesday, 23 February 2010, 18:49 IST
Bangalore: Programmable logic solutions provider Xilinx has unveiled its architecture for next-generation FPGA products that will be built on 28 nanometer high-k metal gate at TSMC and Samsung. Using this process the company aims at FPGAs that can deliver 50 percent less static power than they would if a standard processes were to be used.
Xilinx believes reduction in power consumption is critical for enabling customers to stay within their cost and power budgets as they use FPGAs to meet their system integration and high-performance targets. A scalable, unified architecture based on the fourth generation ASMBL technology will be used throughout the product line to reduce customers' investment migrating designs from older generations, while easing the development and IP use in new designs.
Today, there are challenges such as the high cost of designing and manufacturing ASICs, rapidly evolving standards, the need to reduce bill of materials and the need for both hardware and software programmability. All of this in the face of rough economic times and reduced staffing - are converging to create an environment where electronics product designers are increasingly looking to FPGAs as alternatives to ASICs and ASSPs. "The Programmable Imperative is Xilinx's way to describe the confluence of trends that is resulting in the need for programmable logic in electronic systems," says Suresh Menon, Vice President, Product Development, Xilinx.
According to Xilinx, the lower static power provides its customers with the lowest-power FPGAs in their class, and contributes to a 50 percent reduction in total power compared to previous generation devices. Meanwhile, next-generation development tools reduce dynamic power as much as 20 percent through clock management. Enhancements made to Xilinx's partial reconfiguration technology will enable designers to further drive down power consumption and lower system costs by 33 percent, claims Xilinx.
Tool enhancements deliver productivity gains in alignment with a unified ASMBL architecture that reduces the need to modify a design to accommodate moving between the range of high-performance and low-cost devices, says Xilinx. And ease design migration as Spartan-6 and Virtex-6 FPGA customers transition to the development of their next generation products over time.
Xilinx's collaboration with ARM on the next generation AMBA AXI specification with extensions for FPGA implementation, announced in October 2009, will further drive IP development and re-use by providing software and hardware designers with a proven, broadly adopted standard for interconnecting IP blocks and building embedded systems. The initial devices will be available in fourth quarter of calendar year 2010 with initial tools support available in the ISE Design Suite in June.
