Cadence unveils integrated chip planning and implementation solution
By siliconindia   |   Wednesday, 10 June 2009, 23:03 IST   |    1 Comments
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Cadence unveils integrated chip planning and implementation solution
Bangalore: Cadence Design Systems, a company that deals in global electronic design innovation has unveiled a solution that provides design and implementation engineers with higher visibility and predictability of chip performance, area, power consumption, cost and time to market across the full array of design activities. This automated approach to semiconductor design has been attained through the integration of Cadence InCyte Chip Estimator and the Cadence Encounter Digital Implementation (EDI) System technologies. The combination of these technologies increases the predictability of key metrics from design specification through final implementation while reducing overall IC project risk. "As development costs of complex SoCs continue to skyrocket, manufacturers in all sectors are looking for increased visibility into their design processes," said Richard Wawrzyniak, Senior ASIC/SoC Analyst at Semico Research. "Cadence addresses a growing industry need by offering a solution that provides a unique and timely window into the development of a SoC," he added. Decisions made during the architectural planning stages of the design round largely establish the chip's resulting size, power consumption, performance and price. During such early stages design teams can recognize the benefits by considering and quantifying a range of architectural and IP options prior to final design, implementation and signoff. The new Cadence solution eliminates guesswork and offers a data-driven and holistic path to the optimization of IP selection and integration. Using this solution, designers can accurately estimate the die size, power and cost, including real-time IP and manufacturing process what-if analysis to ease IP selection and establish design architecture and feasibility. The solution also leverages the huge ecosystem of IP at the ChipEstimate.com portal where over 200 IP suppliers and foundries provide data to allow accurate what-if analysis capability. Once system-level trade-offs and architecture is complete, designers can move to the final implementation phase, leveraging estimates as a seed and driving to faster convergence. The new solution will be demonstrated at the Design Automation Conference in San Francisco in July and will be available later this year.

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