Processing .....please wait.. 
The article has been forwarded.... 
Cavium's new processors to come with MIPS64(R) architecture
By siliconindia
|
Tuesday, 18 May 2010, 00:03 IST
Sunnyvale, California: The new OCTEON(R) II CN68XX/67XX processor families introduced by Cavium Networks will be powered by MIPS Technologies' MIPS64(R) architecture. The new processors integrate 8 to 32 enhanced MIPS64 cores with up to 48GHz of 64-bit compute power in a single chip.
The new processors can deliver high performance and application acceleration for borderless enterprise, mobile internet infrastructure, secure data center and cloud computing applications. They have a high level of power efficiency with new technology that dynamically adjusts power based on the application-level processing requirement.
"Through our close relationship with MIPS Technologies and the openness and flexibility of the MIPS(R) architecture, we are delivering groundbreaking processors with an unprecedented level of compute power. We are seeing increasing adoption of our OCTEON processors among a wide range of Tier-1 companies. We are also aggressively expanding our served markets across the Enterprise, Data Center and Service Provider segments." said Syed Ali, President and CEO, Cavium Networks.
Cavium's MIPS-Based(TM) OCTEON II products are supported by more than 50 tier-1 partners providing operating systems and tools, software applications/stacks, debuggers, complementary silicon, ATCA and hardware appliances, consulting, and other products and services. "Cavium Networks is creating some of the industry's most advanced products for networking, communications and storage applications," said Sandeep Vij, President and CEO, MIPS Technologies.
A new performance standard will be set for the 64-bit MIPS- based embedded processors with the MIPS 64 architecture. It incorporates powerful features, standardizes privileged mode instructions, supports past ISAs and provides an upgrade path from the MIPS32(R) architecture, while providing a solid high-performance foundation for future MIPS processor-based development.
