Anup V Korde
Current
Reasurch and Development
Education
B.E ELECTRONICS
Industry
Semiconductors/Electronics
About Anup V Korde
I spent about 5.5 Years in VLSI (Analog/RF Layout,EDA,CAD,PDK) Industry.Throughout my career I have done Twelve(12) IC Layouts and Designs using CMOS, BiCMOS SiGe, GaAs (MESFET, PHEMT, HBT) of 20nm,28nm, 90nm & 180nm technologies.
I have done B.E(Electronics) from Y.C.C.E College of Engineering Nagpur in 2007.
I have done B.E(Electronics) from Y.C.C.E College of Engineering Nagpur in 2007.
Anup V Korde ’s experience
R&D
at
Cadence Design Systems
, Delhi, INDIA
January 2008 – March 2013
Industry: Semiconductors/Electronics
Functional area: IT Sw- Embedded / EDA / VLSI / ASIC / Chip Design
Working With 20nm & 14nm DRC rule support for VSR & DRD, In that
I am doing the activity to take the constraint specification from
the foundry and test these by adding in to foundry rule or in
design specific rule, write these rule into the .rul file and
test these with physical platform. Handling the Multipatterning
activity for 20nm and below nodes. My current project on the
Derived layer and nested derived layers for 20nm and below
technology with different operators.
I am doing the activity to take the constraint specification from
the foundry and test these by adding in to foundry rule or in
design specific rule, write these rule into the .rul file and
test these with physical platform. Handling the Multipatterning
activity for 20nm and below nodes. My current project on the
Derived layer and nested derived layers for 20nm and below
technology with different operators.
Anup V Korde ’s education
B.E [ELECTRONICS],
YCCE NAGPUR [2007/June]
, NAGPUR
Anup V Korde ’s additional information
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