Durga Sreepathy
Current
Physical Design Engineer
Education
B.Tech/B.E. Electronics & communication
Industry
Semiconductors/Electronics
Durga Sreepathy ’s experience
Physical Design Engineer
at
QUALCOMM India
, Bangalore, INDIA
July 2011 – Currently Working
Industry: Semiconductors/Electronics
Functional area: IT Sw- Embedded / EDA / VLSI / ASIC / Chip Design
ASIC Physical Design - Chip Level & Block Level Designs
Sr. Physical Design Engineer at Rapidbridge/QThink Technologies , Bangalore, INDIA
August 2010 – June 2011
Industry: Semiconductors/Electronics
Functional area: IT Sw- Embedded / EDA / VLSI / ASIC / Chip Design
Expertise in ASIC - Physical Design
IT Analyst/Physical Design Engineer at Tata Consultancy Services , Bangalore, INDIA
February 2008 – August 2010
Industry: Semiconductors/Electronics
Functional area: IT Sw- Embedded / EDA / VLSI / ASIC / Chip Design
Expertise in ASIC - Cell Based Place & Route for Block Level
Design. Involved in Floorplan, Power Plan, Placement, Routing
flows, Pre Mask & Post Mask ECO’s for Semi Custom Physical
design. Good in Timing Closure & Synthesis Knowledge. Custom,
Mixed Signal Layouts
Design. Involved in Floorplan, Power Plan, Placement, Routing
flows, Pre Mask & Post Mask ECO’s for Semi Custom Physical
design. Good in Timing Closure & Synthesis Knowledge. Custom,
Mixed Signal Layouts
Durga Sreepathy ’s education
B.Tech/B.E. [Electronics & communication],
VTU [June,2006]
, Bangalore, INDIA
MBA/PGDM [Project Management & CRM],
MBA [January,2010] , Bangalore, INDIA
Durga Sreepathy ’s additional information
Interests:
Expertise in ASIC - Cell Based Place & Route for Block Level Design. Involved in Floorplan, Power Plan, Placement, Routing flows, Pre Mask & Post Mask ECO’s for Semi Custom Physical design. Good in Timing Closure & Synthesis Knowledge.
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