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There-Is-No-Market-For-Second-to-Market
Aurangzeb Khan
Friday, February 2, 2007
Globalization and consumerization—these two trends have defined the demand for electronics products in recent years. From automotive, industrial control, consumer to IT, networking and wireless, the electronics industry looks healthy across many sectors. This bodes well for the semiconductor industry which supplies chips and related technology that power electronics products.

Of all the markets however, the three that stand apart are computing, consumer, and communications. Together, they consume the majority of the semiconductors manufactured and, according to Semiconductor Industry Association, show a healthy CAGR through 2009. Of these, consumer electronics and wireless communications now consume the greatest number of IC’s; on track to exceed $110 billion by 2010 according to Gartner. This trend is driving a sea change in how products are developed and consumed. Why? Because time-to-market and time-to-volume are now critical. If a company is second to market with its product in the consumer space, chances are that product will have no market.

Design complexity also continues to increase on many fronts, along with technical requirements. For example, power management is a concern for most market segments, especially with SoC’s (system-on-chip) developed in advanced process nodes such as 90nm and below. As we move down the feature size curve to provide more functionality, power optimization becomes increasingly critical. This is particularly true in the consumer, computer and communications markets.

The semiconductor industry depends on the efficiency of electronic design automation (EDA) tools, which enable smaller, faster, cheaper and more capable next-generation electronic products. And the changing market dynamics and technology needs require a new approach to electronic design.

What’s the big story in 2007?
The big stories for the worldwide electronic design industry this year will revolve around the emergence of a true enterprise level capability to optimize the interrelated development challenges faced by systems and semiconductor development teams, and the solutions developed to enable their vision. Challenges like power, verification, manufacturability, and schedule will require customers to look at the enterprise picture.
The year 2006 saw companies across the product development value chain coming together with the goal of enabling the design and production of more power-efficient electronic devices.

Called the Power Forward Initiative, this industry coalition launched a standards effort to create a consistent Common Power Format (CPF) for representing IC power intent. The need for a standard is driven by the fact that, today, there is no single, unified way to specify power intent and communicate that intent holistically throughout the design flow. The result is a fragmented design flow which is error prone and extremely difficult to automate.

The initiative draws from the collective expertise of leading technology companies such as AMD, ARM, ATI, Cadence, Fujitsu, Freescale, NEC, NXP and TSMC, to name a few. Power Forward Initiative members are already working to validate the Common Power Format (CPF), a new open specification language that captures all power-specific design goals in a single file.
We expect further progress on this front as this will help the electronic industry move to a more systematic, integrated approach towards low-power design.

Another area is the emergence of a system-level design and verification infrastructure that enables low-power design, significant IP reuse, and comprehensive verification. As electronics continues to become common even in traditionally mechanically-oriented products, both chip and system-level verification become significant economic factors.

A platforms and derivatives approach to design has become increasingly more important. Platform-based design, in which the chip’s architecture is optimized for a specific type of application, seems to be one viable solution to addressing design complexity in a fast-moving market. While the use of a platform may limit choices, it does enable extensive design reuse and therefore provides faster time-to-market.

Providing an integrated approach to design (holistic optimization, all the way from applications, software, architecture, hardware design, including IP, to devices and process technology) is required for the development of such products. Cadence offers vertical ‘Kits’ which provide a new level of integration: A Kit is a set of platform flows applied to a market-representative reference design, enabled by IP and packaged with applicability consulting. Chip design teams are using kits to quickly ramp up design infrastructure and achieve shorter, more predictable design cycles.

The manufacturability of electronics is becoming an enterprise-wide responsibility. The ability to analyze and hence correct for and prevent adverse impact from lithographic effects and variation in the manufacturing processes are now integral to the product development process, from system specification and micro-architecture definition all the way through to tape-out and manufacturing release. Product development teams will be looking for an enterprise design system which is manufacturing aware in 2007, to address 65nm and 45nm manufacturability requirements. They will also test the readiness of EDA solutions to support 45nm design and manufacturing.
Today Design for Manufacturing (DFM) is focused on late-stage correction of manufacturing issues. True DFM will emerge as the technology is integrated into the custom/analog and SOC/digital environments. Like power, some of the manufacturing challenges are best addressed during the micro-architecture, design and implementation stages, but the information necessary to enable this has to be shared across teams and tools in a consistent way.

The challenge is to provide the complete and integrated design and implementation infrastructure necessary to support optimization and prevent recurrence, which is what next generation DFM requires.

On the business front, cooperation and partnerships among semiconductor companies will prove critical to their success in the global design ecosystem. Manufacturing capitalization and technology development costs are driving consolidation in manufacturing technology and capacity. We already know of such alliances. At Crolles2, a joint 300 mm (12-inch) wafer manufacturing facility and research and development alliance in Crolles, France, Freescale, ST Microelectronics and TSMC are sharing the cost of developing advanced technologies to speed time to market. We foresee more such partnerships.

In terms of geographic growth, Gartner predicts the Asia-Pacific region will cement its status as the centre of the global semiconductor industry during the next five years, as manufacturing, consumption and intellectual property (IP) development will be increasingly concentrated in China and India.

Small form factor, long battery life, high-bandwidth wireless connectivity, data bandwidth—these are the challenges electronics companies face every day, and these are the challenges the semiconductor and EDA industries must help address so that new products continue to provide the value expected by the billions of us around the world who rely on technology every day.

The author is Corporate Vice President, Cadence Design Systems, Inc.
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