Hardwired for Success

The conference room at the Open-Silicon office in Milpitas, CA is fast transforming into a 'Deliberation Chamber'. A consultation on the nuances of a silicon chip upgrade between the company's design team and the product architects of their IDM client is fast gaining momentum. One of the architects, evidently oblivious to the animated discussion surrounding him, reaches out for a notepad and quietly begins to define the upgrade that will soon be his company's next generation product. Talks levitate to action-the embedded micro-processor needs replacement along with the interface, number of video channels need to double, the audio processing unit needs to be able to handle Dolby surround sound, internal memory size needs to cope with real time video streaming and so on. Within hours, the team has a Gantt chart showing dependencies and timelines of various tasks that would have to be done to create the final product. Such scenes are played over many times at a company that thrives on transforming Ideas into Products that make a difference in the lives of millions of people worldwide.

Needless to say, there is a clear rationale why many OEMs and IDMs want to engage with prominent players such as Open-Silicon for chip-design as opposed to doing the design in house. To pursue a successful design within their organization, a company would have to get through a long check-list that is both arduous and risky-from hiring competent designers with correct skill-set, to purchasing tools, to overseeing contracts with various vendors, to making sure they are covered from prospective legal 'liability' that may arise while buying Intellectual Property (IP). Through the knowledge gathered over 100s of years of combined experience in designing chips, Open-Silicon takes care of all such risks of creating an ASIC from specification to high volume manufacturing. "At Open-Silicon we take care of everything from scratch to finish, allowing the clients to focus on selling their products rather than making them," assures Taher Madraswala, President and CEO of Open-Silicon.

During a recent project with an IDM client, Open-Silicon delivered a seamless upgrade to a product line in 14 months-beginning from the base design of an older product. The number of wires that the Open-Silicon designers had to maneuver through in the chip were tenfold of that found in a Boeing aircraft. "A delivery time of 14 months is ant-years in the semiconductor space," states Madraswala. Such an accomplishment is by no means an accident; it's by design, achieved through years of experience and skills honed along a long road. In order to truly fathom Madraswala's 'ant-years' statement, one must delve deep into the path adopted by Open-Silicon and the intricacies involved in successful chip design.

Open-Silicon has shipped over 115 million chips. The company has over 310 designs under its belt, having worked for more than 150 unique customers from tier-one system manufacturers, and Fortune 500 companies to startups. "Our clientele ranges from networking, computing, consumer and mobile, to tele-communication, storage, digital signal processing and more." The company's designs have been implemented in approximately 100 different end applications ranging from network processors and aircraft flight display electronics to digital cameras and wearables.

Robust Methodology Reduces the Risk

Every chip typically has a processing unit and a memory unit, between which, data goes back and forth. There are pre-fabricated standard interfaces that every chip normally has in order to bring data in and out of the chip. Universal Serial Bus (USB) for instance, is a standard protocol that can be implemented in several ways. "The entire IP ecosystem has been built around well-defined specifications, which are written and approved by standards committees," says Madraswala. "With regard to USB, let's say a client has the requirement of a dense USB macro occupying the smallest possible area in the die, or the USB needs to be at the edge of the die or the center of the die. Our engineers have a thorough understanding of such needs and can implement the desired result based on customer needs." The same philosophy is applied for requirements such as lowest possible power consumption and/or high performance.

"A wrongful selection of the constituent parts of a chip can risk the working of the entire chip," states Madraswala. "Leveraging our expertise gained through practice and research, clients can zero-in on the best performance for their specific application." The company, shares the entire risk profile of choosing the IPs by grading them on a scale of one to five. A highest grading of five indicates that the chosen IP has seen high-volume manufacturing in chips across multiple domains. "The more the IP has been used, the lesser the risk involved and the greater the odds of reaching high-volume manufacturing quickly," says Madraswala.

There are also instances, according to Madraswala, when a client wants to choose a vendor who may have oversold an IP's performance and did not thoroughly describe the risk involved in using that IP. The team at Open-Silicon will use their qualification process to inform the client of any facts that the IP may pose, like a risk of not having seen high-volume manufacturing even though it may have some innovative features. "We share the risk involved with our customers after which it is up to them to decide which way to go," says Madraswala. "The crucial aspect here is-now, the risk is calculated rather than blind."

Open-Silicon applies an open business methodology that empowers clients to choose the best-vendors, IP blocks, design methodologies and tools, manufacturing, and test capabilities. The company optimizes the chip supply-chain through a wide portfolio of pre-qualified IP, test solutions, products and design engineering. The essential differentiator for Madraswala's company comes to the forefront when customers come to Open-Silicon for the design of a chip on a specific market domain. "Having had the privilege of implementing a chip for that domain in a different kind of a chip or architecture, we can assist our customer in the decision-making process," says Madraswala. The Open-Silicon experts guide the client in the selection of the right pre-fabricated blocks that will make up their specific chip.

"We are the supply-chain managers for all the vendors that are involved in the manufacturing of an ASIC. Once the chips are manufactured, we also manage the worldwide shipment of the units to their assembly ports"

The Open-Silicon methodology brings into play a set of rules and check-lists. Additionally, in order to rule out any potential human error, the company automates most of its checking process. "Our designers write 'value-added wrappers' on top of the industry tools that we leverage to design the chip," says Madraswala. There are hundreds of ways to use a given set of tools. Turning the right knobs to extract maximum efficiency out of the tools is an art. Through the value-added wrappers, the Open-Silicon team has unraveled the most optimum settings of the tools, which helps reduce the risk of failure and maximize the level of success. "This is what we offer to the industry and share with our customers," states Madraswala.

With the aim to deliver quicker, cost-effective designs, Open-Silicon has established Technology Center of Excellence (TCoE) to help integrate complex IP subsystems. TCoE improves time-to-market and design quality with access to world-class front-end and back-end design capabilities, IP integration, and packaging and test services. "This initiative enables Open-Silicon to engage with customers at every level of design and address their challenges comprehensively, ensuring they meet their power, performance and time-to-market goals," says Madraswala.

Dotting the 'i's and Crossing the't's

Before moving into high-volume production, most companies go through the process of 'stepping', which involves at-least two to three revisions of the chip. The norm in the industry is that the chip is almost never ready for mass production when it first comes out. "The stakes are high in chip design, and with growing complexity, all the i's have to be dotted and t's crossed," asserts Madraswala. Open-Silicon makes it a point to ensure that the chips designed by their team are ready for mass-production after the first prototypes are built. "We have two well-defined metrics steadfastly tracked by our experts and shared internally with our Board and externally with our customers," says Madraswala. 'Reliability' is the metric that measures whether the chip works satisfactorily after the first testing. The industry standard of the triple-stepping process to achieve a clean version of the chip yields a reliability metric of around 60 to 70 percent. "With our methodology, we've maintained a reliability guarantee of up to 93 percent," prides Madraswala.

Predictability is the other metric that measures the schedule aspect of the chip delivery. "We monitor this metric on the basis of what we've promised the customer and what we deliver," explains Madraswala. Broadly, the industry predictability rate, ranges between 35 to 40 percent. "We deliver prototypes 80 percent of the time within the scheduled window."

Once the chip is designed to the customer's satisfaction and delivered on-time, the focus shifts to the manufacture of millions of units and its shipment. "We are the supply-chain managers for all the vendors that are involved in the manufacturing of the chip. Once the chips are manufactured, we also manage the testing and shipment of the units worldwide." A common chink in the armor when it comes to the shipment process is a measure termed Defective Parts per Million (DPPM), which is the average number of defects found for every million parts that are shipped. The industry norm for the silicon chip DPPM rate varies between 200 and 300, meaning for every million units shipped, 200 to 300 defective units are acceptable. Open-Silicon maintains a DPPM of 30, a tenth of the industry standard. "If a part has left our test house, you can be rest assured it's almost never coming back," assures Madraswala. As a testimonial to his statement, a popular TV maker in Japan required the DPPM to be less than 10 throughout the shipment process. Open-Silicon successfully honored this agreement clause through 32 million parts that were shipped to the customer serving this TV maker!

We are the 'Implementers'

Madraswala is well aware of the fact that companies are often reluctant to outsource designs due to a prevalent fear of IP leakage. "We maintain well-placed processes and infrastructure to protect the customer's IP to ensure that it never leaks out," confirms Madraswala. The company has erected a three-layer protection system in its server farms. In addition, ample caution is exercised in the manner in which the internal team is assigned to view the client's data, and in the style of internal communication within the team. "We've served over 185 customers without a single instance of malpractice," says Madraswala. "We guarantee the security of a customer's IP."

When the risk of attempting innovation is high, visionary designers and industry newcomers can translate their ideas into real platforms by working with companies like Open-Silicon. The semiconductor industry is innately dependent on continuous innovation, and exorbitant costs cannot be allowed to create barriers that keep the sector from pursuing the development of more complex architectures.

The industry is transitioning very quickly from innovating at the hardware level to the application level. "The writing's on the wall," states Madraswala. "Our industry requires idea managers, innovators and inventors." From self-driving cars to virtual reality, Madraswala suggests that the inventors and idea managers should invest their time into defining ground-breaking concepts. "Our team at Open-Silicon, through our experience, will implement it for them," assures Madraswala. "Irrespective of what your requirements are, we will implement it for you. You dream-on and we will translate those dreams into real products."

"We can guarantee the security of a customer's IP and get a chip implemented at half the cost what it would take a large organization to do"

Industry estimates indicate that about 6000 new silicon chip designs start annually, half of which come from the big players. "We currently have the capacity to do 12 to 15 Application Specific Integrated Circuits (ASICs) every year across myriad market domains," says Madraswala. "We believe that there is a huge opportunity for us to grow for the foreseeable future."

Key ASIC Portfolio

Specification to Chip (SoC) IoT ASIC Platform

The emergence of Internet of Things (IoT) is creating the opportunity to move from off-the-shelf chip designs to custom silicon. "The key to creating cost-effective, custom silicon for the IoT is the platform approach," believes Madraswala.

Open-Silicon's IoT platform includes pre-designed register-transfer level (RTL) of field-proven components along with a support ecosystem of software and services for a variety of protocols, operating systems, and analytics. The design is scalable and allows for variations in hardware/software partitioning as well as the integration of custom IP. Most of the hardware blocks are designed, and associated software already developed; the project can therefore begin at a point, months ahead of a full-custom design. "For IoT developers," Madraswala insists, "ASIC afforded product differentiation and added security are more valuable than low cost."

Virtual Prototyping

In the last few years virtual prototyping has become a mainstream component of Open-Silicon's SoC design. "Companies who invest in the right virtual prototyping tool are finding that they can quickly develop fully functional virtual prototypes with moderate effort," observes Madraswala. Consequently, software quality is improving because virtual prototyping systems allow more lengthy automated software testing. Through Virtual prototyping, Open-Silicon brings three key benefits to clients: faster time-to-software-development; improved software quality, and lower development costs.

High Bandwidth Memory and 2.5D ASIC SiP

"An early investment from us allows us to offer 3D memory stacks integrated into the ASIC package using silicon interposer 2.5D technology" says Madraswala. The result is higher performance, lower power and a smaller form factor system-a three way win. 2.5D and 3D stacking creates ways to mix and match chip-components, meaning products can be divided into multiple dies so that some functions can be at a less expensive process node, mixed with other functions that require a high frequency or new low power technique. Open Silicon's high-bandwidth memory (HBM), enables 1024-bit wide memory paths to ASICs using 2.5D system in a package (SIP) solution. "Anyone with an ASIC idea can improve their access to memory by applying Open-Silicon's HBM SIP approach including the necessary IP and using JEDEC-compliant HBM memory chips, which come in stacked-die 3D versions," assures Madraswala.

Testaments of Success

Camera Consumer Application:

In one instance, a Tier-1 OEM required a mid-range to high-end Camera SoC application with specification to silicon, architecture analysis using Virtual Prototyping and FPGA for early software development. Using a 28nm technology process, Open-Silicon delivered a low power design and refined the architecture before the RTL development started.

Wearable IoT Application

For an IoT Custom SoC-Wearable Device, another client engaged with Open-Silicon who took over the physical design (jointly with the client) and manufacturing along with Post Silicon validation. Utilizing the 180nm technology process, the company developed over 300 validation test cases that included system performance and stress testing to successfully combine several standard products into a single SoC.

Smart Appliance IoT Application

Another Tier-1 OEM, for a Home Smart Appliance-IoT Custom SoC, required FPGA Implementation for early software development along with Architecture, RTL Design/Integration and Verification. Open-Silicon delivered low power design with support for Dynamic Voltage and Frequency Scaling (DVFS), Low-Dropout Regulator (LDO), various power domains and power modes with a 55nm technology process.