Cost efficiency: The Smart Trend Gaining Ground in EDA
Date: Monday , March 29, 2010
Greater cost of developing new chips (upward of $100 million) is pushing certain trends in the industry. Verification continues to be a big challenge. There is more consolidation in functional verification methodology and more formal planning and automation for verification. Among the beneficiaries of increased chip development cost are the FPGAs. However, due to increased complexity, here too verification is becoming more of an issue. Increasing costs in EDA is making big customers go away from single source providers to multi-vendor methodology and tools. Reducing cost and increasing efficiencies is in focus. The importance of Indian outsourcing has gained momentum, and companies are now creating strategies to work with the new realities of the ‘flat world’.
In my crystal ball I see innovation leaders emerging from the flat world. The cost difference that promoted outsourcing will disappear. Verification and embedded software development will continue to play a central role in system development. Winners will be companies and individuals that reduce cost by automating and creating efficiencies through the entire design and development process.
For entrepreneurs, challenges and opportunities are two sides of the same coin. The economy may go up and down for some time before it reaches a new plateau. Until then the smart entrepreneur will capitalize either way. When the economy is going down, concentrate on the internal workings and operations, make the organization a lean, mean, cost conscious, highly innovative machine. And when the economy picks up, expand and sell to the widest possible base. We have found that some of the apparent advantages that the big companies have are actually albatrosses around their necks, smaller startups don’t carry that baggage and can be more agile and maneuver well in a troublesome economy.
Anupam Bakshi is the Founder and CEO at Agnisys. Agnisys Inc. is a developer of electronic design automation tools for the design and verification of IP, System-on-Chip (SoC), ASIC and FPGA.