Dham: Beating a New Path
Date: Sunday , July 06, 2008
CAESAR, VINOD DHAM’S GOLDEN-HAIRED Labrador, is given to loping around Dham’s hilltop estates in Fremont, CA. He wears a collar with an embedded chip, and you wonder if it is to stop him from crossing over the estate boundaries. “No,” says Dham. “It is his key to the house. The trapdoor has a detector in it, which reads the chip and opens up to let Caesar in. Other vandal animals can’t come in.” What else would you expect of this legendary chip man? “Oh! There are many other such smart things around here,” laughs Dham. “I love the intelligence in chips. One day, they will pervade our lives, in ways we haven’t yet seen or imagined.”
Dham has spent the last three decades in the semiconductor industry, and needs no introduction. Following successful stints at Intel and AMD, he went on to head a startup, Silicon Spice, where, as he says, “the technology excited me.” After a quiescence that followed the acquisition of Silicon Spice by Broadcom, Dham is now back in the game. An equal partner with Tushar Dave in a newly founded venture firm, NewPath Ventures, Dham and Dave are building shell companies in the U.S., that would source the majority of its development work from India, and use the Far East Asian foundries to establish design in silicon. “The U.S. is the market, India has the talent, and Asia has sufficient economic capacity. Why not marry all three?” asks Dham.
siliconindia speaks to the “father of the Pentium” on some key issues.
Current semiconductor process technologies in vogue are CMOS and Gallium Arsenide. Next generation technologies being talked about are SiGe, SOI, Copper, low-k dielectrics and compound semiconductors. How are these technologies going to influence the semiconductor industry from a chip design perspective? How will they bring changes from a customer and supplier perspective? Will any of these become mainstream in the next 10 years?
I see silicon still being the dominant technology for the foreseeable future. The process technologies that you mention are still only part of the entire technology integration, with specific uses like decreasing resistance, leakage control, and so on. The technology has traditionally been described by the underlying substrate. This substrate has, for long, been silicon, simply because silicon dioxide is by nature the stablest of materials, which has led to economically favorable process technologies. You also have to contend with the lack of friendliness in the other substrates when it comes to process, and these substrates thus have never moved beyond niche uses. From a mainstream point of view, I think silicon will be the leader for some time to come. In fact, one of my first projects in the U.S., back in 1977, was to develop silicon germanium epitaxial layers, and the technology has been around for a long time. The very fact that it hasn’t seen wider mainstream application in more than two decades speaks for its limited success.
Next generation semiconductor fabrication technologies are pushing 300mm (12”) wafers and 90nm (0.09micron) line widths. What are the implications of this move from a semiconductor equipment/fabrication and chip design perspective going forward? What are the cost performance tradeoffs that will have implications on the manufacture of chips and the chip design community?
A very good question. If you go back a decade and more, we have moved from 3” wafers to 5” wafers, and then to 6”, 8” and now 12” wafers. This is a very natural progression. The large wafers give you reduced costs and reduced yield-per-die. In same lien, the progression from 0.13 micron to 0.09 microns is also natural. But this time around, it is very different in two regards. Even though this is a natural progression, it has hit a critical inflection point, where the capital required to put together a fab at 0.09 micron is so prohibitive, that it already hinders its proliferation. This is pushing companies to join forces so that they share costs in this very expensive progression. This in itself is a change. Not readily evident, and more fundamentally, we are reaching a critical point in the size of the die wherein the optimal die size on these very large 300mm wafers is getting larger than our ability to meaningfully come up with new functions to utilize this large die. The gap between the available technology and our ability to exploit this technology has widened drastically.
Another change that is not widely discussed is the fact that, like many other inventions—telephone, radio, television, and automobile—the semiconductor is also reaching new levels of pervasiveness and saturation. I call this the top of the “S” curve, and this again, is natural in the 3 to 4 decades of semiconductor innovation. This saturation is going to engender major shifts in the structure of power in the semiconductor industry. Given the current levels of commoditization of semiconductors, the widespread industry acceptance of the fab facilities for 0.13 and 0.18 micron levels, there is going to be a longer stagnation period in these levels before the industry will move on to the next level.A significant chunk of technology and product will stay in the “older” technology for longer than in the past due to push out in cost cross-over.
Mask costs/fabrication costs have increased exponentially as evidenced by the 130nm (0.13micron) generation. What does this portend for the 90nm (0.09micron) and lower generation in terms of yields and costs? What can the semiconductor world expect in the future?
Companies like LSI Logic are moving away from the fab model and will depend more on foundries like TSMC to deliver their technologies in silicon. Intel seems to be the only one that has historically held on to its fab. But I would not be surprised if Intel is also forced to move away in some cases where they do not dominate and command artificially high margin as in microprocessors. I am not sure if Intel’s cost of fab is any less than the foundries elsewhere, and especially as the demand for their highest performance chips lags due to lack of compelling pull from application software they will be forced to scale back on their huge capital expenditure and increasingly utilize outside foundries. As foundries tend to upgrade manufacturing technologies, they would be able to offer better yield, and thus costs, to client companies.
There are two schools of thought with respect to how the semiconductor industry could evolve. The conventional school of thought is that no single company can—or will be able to—offer the complete set of best-in-class solutions to address all the technical challenges ahead. Instead, chipmakers need a combination of solutions from several sources, requiring innovative business models that encourage co-operation among suppliers even as they continue to compete with one another. The other school of thought is the emergence of a new order, a new company model—the super integrated device manufacturer (IDMs). IBM and Intel are examples of this emerging new order and are expected to dominate not just in chip design but also by dominance of software architecture, a hegemony spanning not only CPU cores but also the instruction set architectures and software development tools. Which school of thought will emerge victorious in this century?
I don’t think the second school of thought can come to fruition. Think about the economics of it. From a pure innovation point of view, it is impossible for such an exercise to survive in the long term and generate profits. In fact, even today, Intel offers only a piece of the puzzle. All the attendant pieces are third-party supplied. Even the largest player would be incapable of vertically integrating all these technologies and delivering an end-to-end solution. In my opinion, the industry will become more and more horizontal. The trend is going to be towards more programmability, where it is no longer one fixed solution, but a fixed piece of hardware (in itself very modular like Lego blocks), with an increasing amount of software layers that deliver the application. This kind of model would be increasingly prevalent in the coming years. With easier licensing models of IP, widely distributed (as opposed to localized) model of software development, the coming decades will dictate a flatter business model.
The EDA industry is going through a resurgence over the last few years and continues to do so in terms of improved tools for conventional functions (synthesis, gate level, layout, verification, etc). Additionally, there is the emergence of “system level” tools and SoC design tools to go from architecture level to gate level. What can one expect in the future from the EDA side of the semiconductor industry?
Let me paint in a perspective on this. If you look at the semiconductor industry today, it is a $150 billion industry. If you look at the EDA space, Synopsys, Cadence and Magma together is about $2 billion, and even if the rest of the internal CAD tool efforts inside the merchant semiconductor companies add up to another $2 billion, the total industry is still only about $4 billion, a minuscule percentage of the semiconductor industry size. The tools industry has barely managed to keep up with the chip industry. I say “barely” because the tool industry has not done a good job of delivering effective tools to engineers—tools that are interoperable, cost effective and user friendly. The user here is not the common man, but engineers who are innovative and creative—who are very adept at fixing things when they don’t work. I think the EDA players will simply be racing to keep up with the semiconductor industry, but may not be capable of delivering any industry-shattering tools. More than two thirds of design effort in new complex designs involves complex testing and verification. With the cost of masks and wafers at .09 micron generations becoming prohibitive, the need for taping out chips that will not require expensive revisions will dictate better and more effective tools for verifying these chips before committing them to silicon. This is the single most important challenge facing the industry.
Do you think the design industry in India will go the services way, as seen in IT? What do you foresee as problems in design out of India?
I sincerely hope not. The problem with the service model is that you are not getting the full value of the product. Creating intellectual property in-house brings extensive value, more revenues, and increasing demand for the product, and thus the company. In the software space, the government could not comprehend the enormity of the business potential or the industry growth, and the rules and regulations for a non-physical entity were made as the industry grew. However, in the semiconductor space, there are physical entities to comprehend, and the rules will differ. However, I hope that with the passing years, these rules are made favorable to the industry and the inherent potential within the industry, that could explode with just laws.
The most intense global competition in the semiconductor industry is emerging from China, which has adopted a three-pronged strategy: to be the world's low-cost manufacturer, the world's foundry, and the world's design center. India is believed to be a wild card in the race, with a huge and growing pool of designers that now includes a significant number of power users—Off-shore Development Centers (ODC) of large U.S. companies—IBM, Intel, Cisco. What are your opinions on these predictions?
Whether it is the U.S., India, or any other country, China is a cause for concern. The sheer scale at which they have grown in the past decade is incredible. If you look at the semiconductor fab industry, 70% of the cost is in capital cost. It is like buying a Boeing 777. Once you have bought the aircraft, you will have to fly it. And as you fly from point A to point B, you might as well seat people in it.
Considering the cost of getting a new technology chip out of the door, we will be using the older technologies in fab for some time to come, and China is a very relevant factor to consider in this scenario. That said, China is not yet there in terms of design strength. It is catching up very fast. India has not taken much interest in chip design, as much as it did in service. Software service models involve low investment and fairly steady revenues. We need to break this mindset, and move to the next level in the value chain. Chip design should be the natural progression for Indian engineers to take up. Today, if you heave a rock in Bangalore, you are bound to hit a UNIX or an Oracle software engineer. Such quality resources should not be wasted in mundane jobs, and should be challenged to innovate, develop, and deliver superior products, that come with the pride of ownership. NewPath’s efforts lie in this direction.
We will see a lot more engineers who are “chip heads,” and not “software geeks.” In that shift lies India’s promise.
How do you see the semiconductor evolving in the days to come?
I think some of the labels like system-on-chip, hardware, and system integration, and so on are a bit misleading, in the sense that there is no one independent evolution. If you look at the whole space, there are three segments: 1. memories—DRAMs and SRAMs, flash and so on—that have been commoditized for a long time, and there is practically no revolution in this space. 2. Then there are microprocessors—PC technologies, which is dominated by Intel, AMD, and so on. This space is very interesting to watch and will throw up new challenges with each passing year. In this space, the compelling software required to leverage the silicon technology is far behind and is creating a lot of pain. 3. The third segment is the ASIC—including proprietary technology like ARM—which holds tremendous promise. We will continue to see innovations in this space.
But overall, the semiconductor industry is likely to grow much slower than what has been predicted in the past. The technology is far ahead of the applications. This is going to be the biggest challenge.