Sequence Design: Driving power-aware ICs
Date: Monday , January 05, 2009
Vic Kulkarni and his team at Sequence Design are tackling the low-power design challenge. The tools, Sequence offers, are potentially a paradigm shift in the way power is looked at in a design. Sequence's leadership in low-power design tools and its particular expertise in RTL power management and power-grid integrity makes it an ideal choice to be selected for Top 5 EDA Vendors list.
With the insatiable demand for functionalities from chips—in wireless, gaming, graphics, mobile computing, and so on—the complexity has gone up. As we get to smaller feature size, standby leakage power increases exponentially. The semiconductor industry has reactively moved from 180nm to the -40nm fabrication. It isn’t just feature size reduction anymore, as the laws of physics have now become very critical. Power, timing, cross-talk effects, and heat have become very tall hurdles, which cannot be solved without tackling the silicon effects. Today's designs require power optimization tools that address power consumption early in the design cycle and reduce time to market. Conventionally, design tools were algorithm driven and the silicon effects were approximated. Now the game is changing.
Sequence looks at the problem of power more holistically. "Power has to be managed at all levels of abstraction. It has to be managed at the micro-architecture level all the way to the final sign-off," says Kulkarni.
"From experience with the traditional approach, it is clear that algorithmic and architectural design decisions have the greatest influence on power consumption. Therefore, any new methodology must start at this system level. As a next generation EDA tools company, we are marrying quantum physics, computer science and electrical engineering to derive new tools for the submicron chip market," he adds.
Sequence Design's Design For Power (DFP) solutions accelerate the ability ofy software give customers the competitive advantage necessary to excel in aggressive technology markets.
Sequence's latest product, PowerArtist, is built upon the foundation of proven Sequence RTL DFP (Design For Power) accurate power analysis technology and Open Access Database. It focuses on trimming power in three key areas: Clock, Memory, and Datapath at RTL where designers have maximum opportunities for power reduction. The power savings achieved through these comprehensive techniques are over and above those achieved during synthesis. Next-generation engines examine the RTL code, prioritize power reductions, and either maximize power savings automatically or guide the user through manual edits within a powerful graphical environment, called PowerCanvas.
Another product, PowerTheater, analyzes and optimizes power at RTL, where decisions are made that determine 80 percent of a chip's total power budget, leading to better results and faster time to market. PowerTheater allows users to begin the design process with a firm handle on power budgets – before synthesis, when it is too late to optimize – and complete projects with verified results that correlate to silicon. It also allows 3designers to inspect and probe the precise areas where power is being wasted.
Today, Sequence design tools are in use at nearly all of the top semiconductor companies worldwide, and in more than 150 companies. Some of its marquee clients include companies such as NEC, Renesas, NVIDIA, Qualcomm, Texas Instruments, Samsung, Toshiba, FreeScale, Matsushita, LG Electronics, AMD and many others. Sequence also actively participates in industry organizations advancing low-power design technologies such as the Power Forward Initiative and holds a seat on the board of Si2.