DFMSim: Predicting errors

Date:   Monday , January 05, 2009

The tools, which set new performance standards for design-for-manufacturability
(DFM) solutions, enable designers and manufacturers of complex integrated circuits to accurately predict and avoid systemic errors that impact manufacturing yields and harm bottom lines.

"It's become very expensive to wait for months to find a mistake in the design or manufacturing process of ICs. Such errors can carry catastrophic cost consequences," DFMSim's chief executive officer Anantha Sethuraman had said at the launch.

In a market crowded with competitors, DFMSim introduced the "virtual factory" tool suite. The suite blends analysis and process simulation capabilities to enable designers and manufacturers verify whether the manufacturing matches what was originally intended.

Founded in 2005, and headquartered in Silicon Valley, with an R&D hub in Germany, DFMSim's technology is already installed at four customer sites across three continents, where it is delivering substantial yield improvements to a mix of foundries and fabless semiconductor manufacturers. The company's customers are tapping its solutions to accelerate their yield ramps and time to market.

Clarity amid complexity

The semiconductor has reached a point where the traditional design-to-manufacturing process is no longer sustainable. Increased chip complexity and rising production costs have prompted companies to consolidate, partner or, in cases, abandon manufacturing in favor of the foundry model. However, despite these partnerships and strategies, escalating costs often undermine the efforts of the best iof players in the space.

It is this space that DFMSim seeks to address.
"As design rules shrink, the manufacturing challenges only increase, which renders conventional Wait-on-Metrology (WoM) solutions completely insufficient and very expensive. Our approach is to pull the problem back early in the process and then turbo-charge the analysis with the full power of modern computational solutions," says Sethuraman.

His company offers what it calls the industry's first software platform that simulates manufacturing with 'real data'. This means that designs can be verified in a low-cost, highly efficient simulated manufacturing environment. Expensive errors can be corrected before production starts. This enables faster chip development cycles, accelerated yield ramps, a controlled process transfer from development to production, and sustainable yield at full production.

"Our advanced simulation technology arms engineers with the capabilities to predict manufacturability and yield throughout the entire process flow. With this critical knowledge, they can proceed with confidence along the manufacturing path, assured that the intended yields match the actual output," Sethuraman added.

The company's initial products include a toolkit for analyzing overlay accuracy in lithographic equipment. There is also a similar toolkit for analyzing critical-dimension (CD) data coming out of metrology. Sethuraman says a future release will add a toolkit for resist analysis that will be able to analyze the settings and results on the steps that come after exposure—development, cleaning, etch, stripping, among other things.

The critical point for the company, as Sethuraman points out, is that Process Compact Models (PCMs) themselves are based not on hard data, but on a simulation using parameters that are in turn based on a simulation. DFMSim's tool will replace these equation-based empirical models with actual process data from real wafers. What it seeks to do, in effect, is create a data-based model of all the systematic yield mechanisms. The data could, then, be coded into PCMs, encrypted, and passed to EDA tools.

Sethuraman says that the result will be model-based EDA tools using reductions of actual equipment data loggings and not empirical equations.