June - 2003 - issue > Entrepreneur
Karthik Sundaram
Friday, June 27, 2008
IF ONE WERE TO UNWIND ALL THE INTERCONNECT wires and metal layers of an Intel Pentium 4 chip, and lay them out in a straight line, it would stretch out to more than 1.4 miles. Imagine all of that sitting on a chip. This lump of copper is bound to create trouble. As a metal, there will be heat generated. You must have heard about the nuclear reactor-type heat generation from laptops. Then there is metal proximity. The density of wires and their proximity cause crosstalk effects. And then there are challenges in power management: Controlling growth in subthreshold leakage currents due to lower supply voltages and, thus, lower threshold voltages; maintaining a near constant supply voltage when delivering (on average) hundreds of amps with a variation in supply current of up to hundreds of amps; and finally handling power surges when large portions of the chip “wake up.” According to the U.S. Financial Times,power delivery and cooling account for 25% of a server farm’s operating costs.

With the insatiable demand for functionalities from chips—in wireless, gaming, graphics, mobile computing, and so on—the semiconductor industry has reactively moved from 180nm to the 90nm fabrication. It isn’t just feature size reduction anymore, as the laws of physics—so far blissfully ignored or approximated—have now become very critical. Power, timing, crosstalk effects, and heat become very tall hurdles, which cannot be solved without tackling the silicon effects. Conventionally, design tools were algorithm driven and the silicon effects were approximated. Now the game is changing.

In 1999, Vic Kulkarni, a veteran in the semiconductor and EDA space joined a startup called Frequency Design which had some excellent knowledge in the interconnect science. Perceving the opportunity in power management and heat control tools for chip design, Kulkarni quickly acquired a couple of other startups in these spaces and Sequence Design came into existence. “As a next generation EDA tools company, we are marrying quantum physics, computer science and electrical engineering to derive new tools for the submicron chip market,” says Kulkarni. “From experience with the traditional approach, it is clear that algorithmic and architectural design decisions have the greatest influence on power consumption. Therefore, any new methodology must start at this system level.”

With the high frequency devices and smaller geometries driving the handset markets, standby power is another looming issue. “Currently, the leakage eats up nearly 30 percent of the battery,” says Kulkarni. “This is a tremendous opportunity for us, as there are no tools in the market.” Sequence has tied up with Toshiba in a partnership, to derive tools for this space, where Sequence will share its knowledge with Toshiba’s silicon and end product resources. “As the power decreases, you would expect the chip to run slower. But the market demand is exactly the opposite. We need faster performances from chips which drain power at very low rates. One volt appliances are setting the trend today,” comments Greg Fawcett, VP of marketing at Sequence.

The libraries and tools that Sequence provides can help designers to analyze the space utilization on the silicon, and assign critical or non-critical components—and thus low or high power resources—to the area. “This is much faster than the traditional iterative approach,” says Kulkarni. The optimal power-consuming algorithm is transformed into hardware, normally by manual means, although time to market pressures will increase the demand for high-level synthesis. “This is clearly a large design space with multiple degrees of freedom, each with its own trade-offs and powerconsumption characteristics.” says Kulkarni.

Signal integrity is a critical issue in the submicron silicon design. With millions of gates switching on and off at incredible speed, crosstalk is a big problem. According to a report by IBS in January 2002, the impact of noise on signal integrity results in up to 50 percent increased probability of chip failure for 130nm and lower chips. “Proper electrical engineering and silicon modeling can fix these problems on the fly,” says Kulkarni. “Sequence is unique in its tools. While many of the bigger players offer tools which are built on approximation of silicon performance and characteristics, we have designed our tools bottom-up.” With 8 patents and another 12 pending, Sequence claims the team and its IP have an edge in the market. “Many of the design issues are from concurrency problems; if a designer solves one problem, another may crop up. We are capable of addressing the silicon modeling, with a deeper understanding and can solve the concurrency issues easily,” says the CEO.

The physical design market is about $1 billion in size, almost 25 percent of the $4.5 billion EDA tools market size. With over $30 million in funding, Sequence today is well poised to tackle the next generation chip design needs. “We have over 100 clients today, and are also exploring tools for the foundry market and fabrication industry,” says Fawcett. One of the products, PhysicalStudio, helps in many of the foundry problems. “Process variation in the same chip, and then across the wafer assume bigger dimensions in the 130nm and below chips. Our tools can help in these platforms.” How important is this space? Well, the Design and Automation Conference in Anahiem, CA, this year has listed power, timing and interconnect as three key issues of the conference. “There are no tools in the conceptual design level. We are building some modeling and analytical tools for the conceptual design,” says Kulkarni.

Sequence has chalked up some impressive clients: IBM, LSI, and Broadcom among others. “The fabrication entry level is touching the $4 billion levels, which is putting many startups off. But with state-of-art EDA tools, prototyping could become cheaper and an easier way to enter the ASIC industry,” says an analyst. With time-to-market pressures dictating the design, there will be an ever-growing need for powerful design tools that could solve conceptual and in-silicon issues. And Kulkarni’s slew of cool tools may just well be what the designer ordered.

Share on LinkedIn