Verification: Why is it Vital? Date:   Wednesday , March 02, 2011 The cost of fabricating modern day System on Chips (SoCs) is escalating with each new process node and runs into millions of dollars. Correcting a design after detecting a fault in a fabricated device and respinning the corrected design in a foundry is no longer a feasible solution because of this escalating cost. Further, each respin is time consuming thereby delaying the introduction of the device into the market, which affects its potential revenue and profitability. As an added complexity, software is increasingly determining significant portions of the SoC functionality as well as its development efforts. Hence, it is necessary that the correctness of the design is fully verified before it is released for manufacture. Requirements of Verification Methodology: Any verification method adopted should be: * Appropriately accurate for verification and software enablement * Appropriately fast, especially in enabling software * Capable of verifying the design under real life signals * Easy for debugging * Capable of verifying both the hardware and embedded software. Since the majority of the devices today incorporate large amounts of software, it is necessary that the design needs to be verified in the software environment that the device is finally going to be operated in. Verification Methodologies: Verification methodologies can be broadly classified based on whether the device to be verified is modeled in software or built as a hardware prototype and whether the inputs driving these are given as software driven vectors, real life signals or a combination of both. The use of a particular methodology also depends on the development stage, which the design needs to be verified. If one were to look at the various verification methodologies available today, one would see at one end of the spectrum, methodologies based on RTL simulation and at the other end methods using emulation boxes. RTL Simulation, although very accurate and easy for cycle based functional debugging, is deemed slow and not amenable for hardware-software coverification when compared to other technologies. For example, verification of a boot function of a cell phone chip would typically take a few days using a simulation technique. As soon as classic RTL simulation is augmented with transaction-level models including processor models executing system software, significant simulation speed up can be achieved. Emulation boxes are very expensive and even though they can be used for hardware-software coverification, they are not fast enough to verify the design in the presence of a lot of application software. Verification using virtual prototyping or FPGA based prototyping, which takes the best of the above two techniques, is fast becoming a popular method for verifying complex SoC devices. Using virtual and FPGA based prototyping one can verify the design in a reasonably short amount of time in the presence of application software and is relatively much less expensive than emulation boxes. The prototyping system can further be classified into virtual- and FPGA-based hardware systems. In the virtual prototyping system, the functionality of the chip is modeled using software models based on standard-based languages such as System C and transaction level models (TLMs). Virtual prototypes can be used for software-driven verification, software development integration and test. Since virtual prototyping is not dependent on the availability of hardware (or the chip) for verification, software development can start 6 to 12 months prior to hardware availability. Software is a highly efficient test-bench component, as it generates relevant scenarios. Having the real SW running during verification allows identification of HW/SW bugs pre-silicon, so they can still be fixed with reasonable effort. In the hardware prototyping system, the entire chip functionality is programmed into a set of FPGAs on a board. The board can be either a dedicated one for the design or an off-the-shelf board configured for the particular project. As the hardware prototyping system can be run at nearly the operating speed of the final chip, the design can be verified in the environment of the application software much of which needs high speeds for operation. Also, since the design is operating with actual signals rather than with test vectors, the programmed FPGA prototype board can be used as a demonstrator of the final chip both for internal confidence building as well as early customer engagement purposes. As pointed out earlier, the software content in SoCs is increasing and products cannot ship in volume until the embedded software development is complete. The hardware prototyping allows the software development team to start development of the software and validate it on the hardware prototype platform much before the actual silicon is available. Further, as the prototype boards are relatively inexpensive, they can be replicated and distributed amongst different software development groups to help in simultaneous development of various application software that will run on the chip. This process of early hardware software integration and test helps pull in the system schedule enabling earlier introduction of the product into the market. Synopsys’ Offerings in the Verification Space Apart from being the leader in the RTL simulation space with its VCS simulators, Synopsys has a plethora of offerings for both virtual- and FPGA-based prototyping solutions. In the virtual prototyping space, Synopsys offers a complete tool set for creation of virtual prototype assembly all the way to hardware-software co-simulation, debug and analysis. Innovator – Powerful tool for the creation, assembly, and execution of SystemC-based virtual prototypes for pre-silicon software development and software-driven verification. * Platform Architect/Virtual Platform - SystemC-based graphical environment for electronic system virtualization that captures the entire product platform and the dashboard for initiating the platform analysis functions. * CoMET and METeor – Modeling authoring tool and simulation environment to design, simulate, analyze, and optimize complex embedded systems and quantitatively evaluate performance while running real software applications. * Virtual Prototyping Models – A broad portfolio including the DesignWare TLM Library, SystemC TLM Models, CoMET/METeor Models, and Pre-Assembled Prototypes that serve as the building blocks for virtual prototypes. * Virtual Prototyping Services: Assistance with building transaction-level models and virtual prototypes for pre-silicon software development. In the FPGA-based hardware prototyping, Synopsys offers both the necessary hardware platform and all the required software tools for partitioning, synthesis, debug and transaction based co-verification. The suite of software tools comprises of: Certify: For multi-FPGA implementation and partitioning Synplify Premier: For single-FPGA synthesis Identify: For integrated RTL debug and visibility UMRbus (C, C++, TCL interface), SCE-MI (TLM2.0 interface) and HDL-Bridge: For transaction-based co-verification The hardware platform is called HAPS (High-performance ASIC Prototyping System) which is a highly flexible board configuration with its ability for stacking of multiple boards in horizontal and vertical directions. This ability along with the availability of various daughter boards designed for specific applications enable prototyping complex systems easily. HAPS comes in different flavours with one, two or four FPGAs targeted towards different applications based on the complexity of the design to be prototyped. The authors are Director Solutions Group and Director Sales Synopsis Technology respectively