Semiconductors in the 21st Century – What awaits us! Date:   Friday , February 02, 2007 With the increasing complexity of VLSI designs (10M+ gates), time-to-market pressures, movement to finer process geometry’s (sub-sub micron) and changes in fabrication and EDA tools, it is clear that semiconductor design and manufacturing as we know it cannot be the same well into the 21st century. The microelectronics industry is facing unprecedented challenges at all levels—semiconductor process technology, fabrication/manufacturing equipment, design methodology and EDA tools. The current silicon technology (CMOS scaling), the engine that delivered higher density and performance at lower power and cost in the past, will encounter fundamental (physics) limiting factors and could be running out of steam below 50nm line width dimensions, with the main limitation being quantum mechanical tunneling through a few atomic layers of silicon dioxide, the miraculous material that lies at the heart of all VLSI technology. However that does not mean scaling will come to a screeching halt. Devices will be pushed further at the expense of process complexity and chip power. It will be expensive to push up the clock frequency near the scaling limit, hence massive parallelism may become the preferred alternative to increase processor(s) throughput. In the next decade though, two opposing forces at work, specialization and consolidation will drive the microelectronics industry. Integration and high frequency capability of scaled CMOS devices enable new, system-on-a-chip applications. Yield and cost issues will be a constant challenge for SOCs. Eventually chip economics can only be justified by increased wafer size like the move to 300mm (12”) wafers which provide >2X die area over 8” wafers. This move entails significant changes in semiconductor manufacturing equipment technologies. While there are numerous new device concepts being explored today, currently none shows the promise to replace Silicon CMOS in the foreseeable future. Today’s VLSI technology based on Si, SiO2 and CMOS is the ultimate outcome of the survival of the fittest and will probably continue to live on for the next decade and beyond. Complete paradigm shifts in the form of phototransistors or molecular (DNA) based electronic circuits may be the way of life towards the end of the 21st century? On the fabrication front …. As the semiconductor industry advances from one technology node to the next, feature sizes continue to shrink and even shorter wavelengths are being employed. This trend is resulting in a number of problems that eventually affect manufacturing yields and hence cost. The traditional method of designing a chip or mask and then “throwing it over the wall” to manufacturing is fast becoming obsolete. With the newer generations of semiconductor technologies the number of mask layers and the finer lithography requirements are resulting in exponential increase in mask costs. Finer sub-sub micron geometry’s are going to result in prohibitive mask costs, which will affect the overall semiconductor business model going forward. Escalating mask and fabrication costs demand a tight partnership between customers and suppliers. By providing solutions that play an integral role in a customer’s success, suppliers assume a greater level of responsibility. On the Chip design front …. Increasing wafer sizes (300mm), finer process geometry’s (60nm) and I/O intensive SOC designs are threatening to commoditize the silicon transistor/gate (10M+ pad limited designs). Paradigm shifts in semiconductor design methodology have a tendency to gradually take hold like the migration from schematic capture to verilog/RTL based design in the early 80’s. Moore’s law continues to relentlessly drive potential transistor counts upward at a 60 percent CAGR. Current 0.11 micron semiconductor technology enables a density of ~5 million gates on a square centimeter of silicon. Average System-On-a-Chip designs today are heavily I/O driven thus resulting in pad limited die cavities in the order of 5 sq. cm, which would potentially imply a 25 million-gate design. It’s like building a 100 story skyscraper brick by brick! Maybe doable but not practical! Some hard realities are setting in for the extreme sub-sub-micron design world (60nm) in the near future, prohibitive mask costs and fabrication NREs. Multimillion gate designs at the finer geometries are making the SOC designs more interconnect centric thus requiring accurate modeling of the interconnect, power density, metal migration, capacitive and inductive coupling, and thermal issues. Large teams are required to accomplish the verification and testing of these SOC designs thus resulting in under achievement in design productivity. Significant changes in chip design (EDA) tools have taken place and are continuing to make strides to accommodate the migration of silicon technologies. The next chip design paradigm should accomplish the goal of significantly simplifying and increasing the confidence of designing and verification of embedded systems-on-a-chip with a higher probability of success, in a short time to market. Platform based embedded systems-on-a-chip are starting to take root for economic and practical reasons rather than conceptual and architectural reasons. If one wants to avoid designing the wrong multi-billion transistor chip with an army for a design team, it becomes a necessity (and not an alternative) for them to look at platform based design for implementing Embedded Systems-On-a-Chip. The continued ability to design and manufacture chips that are faster, cheaper, and better from generation to generation requires the industry to move to the next level of creativity and leadership and put in place innovative business models like DFM, DFT, that encourage co-operation among vendors, suppliers and customers. Growing semiconductor milieu in India …. With most of the top semiconductor powerhouses opening up their India development center, coupled with increasing need for off shoring VLSI services, there has been an ever increasing demand for VLSI talent in India. While India has been a powerhouse for software, VLSI training as part of the education curriculum has been weak and hence there is an extreme shortage of moderately experienced engineers with exposure in the leading edge of the VLSI arena. This is further affected by the traditionally large cost of VLSI tools, especially for the backend. Despite these hurdles, the Indian environment is making great strides in the VLSI arena. Most of the activity has been relegated to front-end VLSI RTL design and verification activity in the services arena. HCL and Wipro have a significant presence in the VLSI services arena. In large corporations like Cisco, Intel and TI, VLSI activity is being extended to porting of existing designs to different foundries thus encompassing backend work. VLSI product firms like Broadcom, AMD, AMCC and Xilinix, and EDA firms like Synopsys, Cadence and Mentor maintain significant presence with their India centers. Top universities like IITs and IISC are developing collaborative R&D centers with industry giants like Intel, IBM and Applied Materials. These initiatives are bound to ensure the emergence of India as a power in the VLSI arena in the 21st century. There are a few semiconductor related product companies emerging from India with reasonable success in the world markets like NSys Design Systems, Poseidon Design Systems, MOS Chip, and Xambala. The potential successes here will create a momentum whereby we could see many more of such companies from India. The demanding requirements of setting up a fab both investment wise and infrastructure wise, raises a question of whether India will be able to compete with the likes of Taiwan and China. Despite the challenges, the outsourcing model with the availability of qualified talent and cost arbitrage portends a bright future for India as a player in the VLSI arena in the 21st century. The author is a 22-year veteran of the semiconductor industry based in the Silicon Valley. His career has taken him to companies like National Semiconductor, Chips & Technologies, IBM Microelectronics and Cirrus Logic, while he has also been involved as an entrepreneur with Cognigine, nSys and Agglut.