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Opportunities for EDA Companies to achieve DFM/DFY below Sub micron

Bikram Garg
Wednesday, October 1, 2008
Bikram Garg
Prior to sub-100-nm technology there was a clear demarcation of work between designers and the manufacturing community. The designer community was targeting for better design performance, more design functionality for the same chip area and the manufacturing community was ensuring that the design intent was met with no manufacturing defect. The design rules acted as a policeman ensuring the layout passed to manufacturer meets the constraints (design rules) for sufficient product yield. The basic design rules were constraints on the minimum width of a pattern and the minimum spacing among the patterns required for correct fabrication. This way the designer was isolated about the processes used by the manufacturer to fabricate the chip. But as the chip manufacturing is moving towards deep sub-100-nm technology such as 65nm, 45nm, 32nm the need to have more hand shaking between the two communities has become imperative to achieve higher yield. The yield has decreased considerably at these scales which might delay the adoption of smaller dimensions. The feature scaling is outpacing the manufacturing process changes. Some of the manufacturing processes are hitting a ceiling and the most critical one is lithography. This opens new opportunities for the EDA vendors to come with new tools and design methodology to help adopt smaller dimensions.

The problems

Lithography: The optical resolution limit of a conventional lithography system with on-axis illumination can be approximated as Rmin = 0.5 ?/NA under coherent light Where ? is an illumination wavelength, NA is a numerical aperture and Rmin is the minimum feature size. And the lithography process resolution provided is R = k ?/NA Where k is the Rayleigh criterion which has touched to 0.35 inspite of continuous decrease of wavelength (193 nm) and increase in Numerical aperture(NA), showing that the feature technology is decreasing faster than the lithography changes. Some of the new lithography technologies to decrease wavelength are not mature to be made part of the manufacturing process. There are experiments going on to increase the NA of the lithography process. The immersion of lens in liquid to increase refractive index thus NA has process issues. Also by increasing numerical aperture(NA) to decrease resolution we are deteriorating the DOF(Depth of focus) which is inversely proportional to (NA) square. As the Rayleigh criterion has hit below .5 there are various resolution enhancement techniques (RET) devised to achieve same patterns on wafer as on the layout i.e. “What you see is what you get”. They are Optical proximity correction(OPC), which modifies the patterns on the mask considering the lithography, CMP(chemical Mechanical Process) processes effect so that the effect of below .5 Rayleigh resolution is nullified, Alternate Phase Mask shift (AltPSM) which passes lights through two source path shifted by ½ ? to have destructive interference resulting in doubling the resolution limit and many others like double patterning, AttPSM and others. Adding these RETs bring in many new complex Design rules and also conflicting rules which are not easy for the designers to understand as this requires a learning curve in technology and also the rules are complex. Thus bringing in strong RET in the processes is a solution but can result in more systematic defects in the chip affecting the yield and economics of the fabrication.

Interconnect: Second major issue encountered due to scaling of features has been the increasing interconnects delay. The function of interconnect or wiring system is to distribute clock and other signals and to provide power/ground to and among the various circuits/systems functions on a chip. With the continued push to smaller geometries based on the Moore law and growing need to improve performance and lower power dissipation in IC, interconnect has become a challenge for feature scaling. The graph below shows how the interconnect delay has been rising with smaller scaling vis-à-vis the device delay. In 100nm the device delay was ~20ps and that of the RC delay of the interconnect of 1mm was ~1ps while in the project 35nm technology the device delay will come down to ~1ps but the RC delay of interconnect will be ~250ps. Not only that the power dissipation in interconnect will also increase to ~80 percent from ~50 percent in the earlier technology. The increase in the interconnect wire aspect ratio together with decrease in the line-to-line spacing results in the increase in the coupling capacitance, increasing power dissipation which is proportional to the capacitance. The increase in interconnect delay is a bottleneck not only to achieve high performance and lower power dissipation in the design but also at the design level the issue of interconnect is more profound. The exact layers and the length of interconnect is decided at the layout level prior to which the designer is done with the design both functionally and in term of performance. The timing information at design synthesis is based on a model of interconnect which is difficult to determine accurately because of distributive nature of interconnect and also the coupling capacitance of interconnect which depends on both the spatial locations of the neighboring wires and temporal relation between the signals on the wire. This can potentially result in iterating back and forth at synthesis and P&R level for timing closure of the chip. This can invalidate the existing interconnect model currently used in the high level designs.
The coupling capacitance can also result in crosstalk which can decrease the signal integrity. The global interconnect such as clock, power, ground requires more thorough handling and modeling to decrease delay by adding repeaters which increases the area of the chip.

EDA Methodologies and Solutions

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