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The Smart Techie was renamed Siliconindia India Edition starting Feb 2012 to continue the nearly two decade track record of excellence of our US edition.

Need to Explore Parallelism, Capability on Multi-core Platform for IC Design Flow Tools

Sachin Pathak
Monday, November 2, 2009
 Sachin Pathak
World is moving towards complex chip design. Various high end devices are required for scientific computing, telecommunication, multimedia, graphics, and consumer electronics. Such state-of-the-art designs require complicated systems and high end IC design EDA tools. Current IC design EDA tools and hardware platforms are over-exhausted to handle the flow, and it takes a lot of time to meet the market. This is affecting the growth of the semiconductor industry and it is restricting us from moving in to a new era of electronics design. The EDA industry has taken a wake up call and has taken a step towards developing parallel and multi-core computation capable IC design tools.

The world of high end technical computing discusses a lot about parallel programming, and focuses on customizing algorithms written to utilize hardware in most efficient way. We always talk about various factors related to high performance systems by introducing multi-core and multiprocessor systems and the growing availability of computer clusters for various high end applications like scientific computing, military, and aviation; but it is time to think about using such high end multi-core platforms and techniques to produce more capable EDA tools to have next generation of complex devices.

If we take a look at history, commercial high end tools to support the development of technical computing applications for high performance systems did not exist. Parallel programming was very rarely used in applications and its development was restricted to a small and technically skilled group of people, and considered as an art applied by specialists who focused on achieving maximum performance by using custom setups and by tuning their applications for specific hardware. Parallel applications like IC design tools are now being developed to assist design engineers in designing, developing, debugging, and evolving hardware and focusing beyond custom algorithms and performance. To achieve success, we need to extend the functionality of standard serial architecture IC design tools used to support parallel architecture multi-core and multiprocessor tools, without extensively modifying the code that leads to a robust IC design and development environment. It is practically impossible to do with minimum change in legacy and stable software code. One of the alternatives for this problem is that we need to force major software rewrites and shift market momentum to a new generation of EDA startups. This option is very expensive and we need to put highly skilled and experienced resources that understand complexity of multi-core programming, if we need to achieve it in given time.

We all acknowledge that multi-core IC design tool support will be essential in the future, and all EDA vendors claim some multi-threading and multi-core capabilities today. But still we need to work hard to incorporate this in various stages of IC design flow from design, verification, synthesis, scan insertion, and Place and Route i.e. physical verification till mask generation to have actual functionality on silicon at various development stages.

Fig. 1 shows how we have targeted multi-core platform use for high end scientific computing devices or intensive computing devices for more efficiency; because we cannot achieve the same throughput from single core systems in terms of various factors, for example time required to complete the job. We need to consider that IC design tools are equally important in this process and need very high attention, if we do not take steps to develop multi-core IC design tools, the entire process of IC design is going to get affected.


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