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The Smart Techie was renamed Siliconindia India Edition starting Feb 2012 to continue the nearly two decade track record of excellence of our US edition.

Evolving Scope of Power Reduction for a System-on-Chip

Somanath Viswanath
Friday, December 7, 2007
Somanath Viswanath
System designers and architects have been accustomed to making feature versus form-factor trade-offs for devices in the mobile product space. Users, however, demand a no compromise experience combined with an extended battery life. Reducing the power consumption of such products has gained sufficient importance to warrant an overhaul of existing System-on-Chip (SoC) design methodology.

Power reduction is one of the primary design constraints for the system architecture and implementation of SoC’s targeted for such products. The effective application of power reduction techniques necessitates the definition of a power specification, portfolio of power reduction techniques, suitable design infrastructure and a robust verification environment.

Developing a robust power specification

Device application and usage models are used by system architects to partition a system into its sub-components, define mission modes, and derive budgets for important design parameters for the system. These characteristics are documented in a functional specification of the system as well as in each component. This methodology should be extended to derive component level power budgets and define a design Power Specification.

Such a power specification is crucial to the successful application of power reduction techniques to a SoC. The specification must be comprehensive enough to enable the verification of the operation of a SoC in all of its mission modes. Designers must also be able to use this specification to verify the implementation of these techniques at each stage.


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