The San Jose, CA-based company's products provide IC designers early visibility into chip design risks and help them get to the source of the problem. Atrenta provides Early Design Closure® solutions to radically improve design efficiency throughout the IC design flow. The company's suite of tools helps eliminate time-consuming design iterations by finding and fixing problems early in the design process. Detecting problems early on means that development costs can be dramatically reduced.
Customers benefit from Atrenta tools and methodologies by capturing design intent, exploring implementation alternatives, validating design descriptions and optimizing designs early, before expensive and time-consuming detailed implementation.

What if you could know, very early in the design process, that your chip would meet timing, perform within the power budget, finish at or below your die size target, achieve quality goals for test coverage and contain no subtle, hard-to-find bugs? Atrenta's SpyGlass and 1Team product lines allow this to happen every day for design teams all over the world.

The SpyGlass product suite analyzes and optimizes designs at the register transfer level (RTL). Basic syntax, or linting, is performed as well as detailed analysis of timing constraints, testability, clock synchronization schemes and power consumption.
Atrenta's 1Team products allow overall design intent to be captured at the architectural phase. Various implementation schemes can be explored, creating a powerful "what if" environment. Capabilities of the 1Team family include semiconductor IP import and assembly, automated interface logic generation, creation of register maps, definition and validation of power and clock domains, and detailed routing congestion, timing and power analysis.

The benefits of this is process, usually referred to as Early Design Closure, are substantial. With over 150 customers, including the world’s top 10 semiconductor companies, Atrenta provides the most comprehensive solution in the industry.