The Smart Techie was renamed Siliconindia India Edition starting Feb 2012 to continue the nearly two decade track record of excellence of our US edition.

February - 2003 - issue > Cover Feature

3D Chips: Future Possibilities

Vivek Subramaniam
Thursday, January 30, 2003
Vivek Subramaniam
OVER THE LAST TWO DECADES, THERE HAS BEEN sustained interest among researchers in the development of a “3D” circuit, namely, a chip technology with multiple layers of transistors stacked over each other (unlike conventional chips, in which transistors are packed in a single plane only). Such an approach would dramatically reduce the chip area, since transistors could now be packed in all three dimensions. Proponents of 3D integration believe that the price of a given chip will fall, since chip costs generally increase with increasing die area. Additionally, it is believed that chips made with 3D technology will have increased speed, since the delay associated with a signal traveling along an interconnect across a chip is often a large fraction of the switching speed of a transistor. By folding the chip over, the average length of the interconnects is reduced (since the chip area is reduced).

Several recent developments have occurred in industry that makes an overview of 3D technology worthwhile. In 2001, Santa Clara, CA-based Matrix Semiconductor, Inc., announced that it was ramping up for production of the world's first commercially available 3D chip technology. Based on the benefits of 3D technology, Matrix claims that it will offer a tremendous cost advantage over its 2D competitors. Subsequently, other companies have also indicated that they are investigating the potential for 3D chip technology.

The transistors in essentially all chips currently on the market are manufactured in only one level for a simple reason—the crystalline silicon wafer can be accessed only "once" during the process. After a layer of transistors is built and passivated, the wafer is completely coated by an insulating layer of silicon dioxide, an amorphous material. It is impossible to grow crystalline silicon on top of this layer. Any subsequent deposition of silicon will result in the formation of polycrystalline or amorphous silicon, which has substantially worse electrical properties.

To get around this problem, various creative solutions have been devised, the most obvious of which is to build transistors in polycrystalline silicon. This is actually a well-known art—the pixel transistors in virtually all liquid crystal displays are fabricated in amorphous or polycrystalline silicon. By carefully controlling the structure of the polycrystalline silicon using techniques such as metal induced lateral crystallization (MILC), various researchers have successfully built fairly high performance transistors in this material. Furthermore, some have actually succeeded in forming crystalline silicon over the silicon dioxide surface using a technique known as epitaxial lateral overgrowth (ELO), in which the crystalline silicon is essentially grown over SiO2 by growing it out and over from a window cut down through the SiO2 layer to the underlying silicon wafer.

There is a problem though—all of these possible solutions use relatively high temperatures to fabricate additional levels of transistors. Silicon is usually deposited above 500°C. The high temperatures steps (dopant activation, gate oxidation, and silicidation) needed to fabricate the second level of transistors would be as high as 1000°C. These temperatures are so high that any transistors on “lower” levels would be destroyed or severely degraded, as would the metal lines interconnecting them. While techniques such as MILC substantially reduce the temperatures needed to fabricate devices, much work remains to be done to produce a fully 3D-compatible transistor fabrication technology. This limit, often called the “thermal budget” limit, is a serious challenge to achieving 3D using this sequential building approach.

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