A Continuous Effort to Solve the EDA Challenges

Power management has become an important criteria and every semi conductor vendor is on the scout for new techniques to achieve better power efficiency. The techniques available and under investigation span the entire design flow, starting from architecture all the way down to transistor architecture and materials, including microarchitecture, design and implementation phases. One powerful technique available for designers during design / implementation is clock gating which was pioneered several years ago. However, maximum benefit is derived when clock gating is implemented at a fine granularity, known as fine-grained clock gating. To save power, clock-gating support adds additional logic to a circuit to disable switching of the clock tree, thus disabling portions of the circuitry when its flip-flops do not change state or do need to change state.. The switching power consumption of the unused portions of the circuit goes to zero, and only leakage currents are incurred. Wasteful switching of clock, logic and interconnect signals is thus saved via the fine-grained clock gating. The challenge however for EDA vendors is to automate this process and deliver significant power savings possible with fine-grained clock gating, while retaining functional equivalence, performance and area. New techniques like Power Island or Voltage Island to deliver increased battery life is being increasingly adopted and is a must for mobile silicon vendors. These techniques enable one to switch off circuits, that are not be required while performing an action, over a given window of time.

Along with Power reduction, the EDA sector is also witnessing continued challenges in verification as the semiconductor process technology node shrinks more and more. The challenge comes as the designers strive to include more functionality into the ever increasing real estate as a result of smaller and smaller geometries. To facilitate the designers, the electronic design automation players have introduced solutions like virtual prototyping and high-speed emulation. These solutions are used to shorten the design cycle, improve product quality, and reduce time to market. The issue of variability too dogs chip designers, who in turn are exploring techniques such as statistical timing analysis. It exploits the statistical distribution of the timing or the performance point of a circuit at a given process node. Designers also realize that they can play with power and performance as variables, thus achieving same performance at lower power or higher performance at the same power point. Hence methods like adaptive voltage scaling and dynamic voltage frequency scaling are gaining ground. In adaptive voltage scaling, instead of feeding a constant high voltage, the voltages fed to the semiconductors are adapted to a lower voltage either statically or dynamically, making adjustments for temperature and other variations, knowing that the silicon can perform within that lowered voltage range without any impact on the performance. While in dynamic voltage frequency scaling, software too plays a part whereby the frequency is first reduced for a given action considering the fact that the action can be performed at a lower frequency without affecting the quality of the operation and the voltage is then commanded to be reduced commensurately.

The four different challenges that the semiconductor industry is witnessing, ranging from power management, verification, variability and stringent design rules, present a challenge and an opportunity for EDA players to innovate and provide better tools, flows and solutions. The big challenge for new EDA vendors is a complete lack of investment by venture capitalists in this sector, while the bigwigs have a majority of the EDA market pie with a plethora of product bundles. It becomes imperative for new and promising EDA players to introduce new technologies to solve any of these customer issues, gain quick customer adoption, and work in partnership with adjacent vendors to broaden the offerings and stay viable.