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Sequence Holds Low-Power Design Seminar
By ST Team
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Tuesday, 05 September 2006, 19:30 IST
BANGALORE: Sequence has recently organized a low-power design seminar in Bangalore. The seminar focused on areas like predicting power consumption early in the design cycle, reduction of switching power consumption, reduction of leakage power, and efficient power-grid design. More than 31 companies including Intel, NVIDIA, Philips, Texas Instruments, and Cypress attended the seminar.
An expert panel comprising Bharadwaj Amrutur, Assistant Professor in the Department of Electrical Communication Engineering, Indian Institute of Science, Bangalore, Rajat Gupta, Managing Director of Beceem, India, Genesis Microchip Lead Physical Design Engineer, Pankaj Panjwani and Virage Logic's Amit Khanuja, Group Leader, discussed the latest in low-power design, its applications in wireless communications and case studies of real-world successes.
Bangalore is fast becoming one of the most exciting design centers in the world. There is tremendous interest in low-power design, and the tools and methodologies required to extend battery life, reduce power consumption, and achieve first-silicon success, said Vic Kulkarni, President and CEO of Sequence .
We look forward to having a long-lasting relationship with the design community in Bangalore, and to making a dynamic impact on their long-term success, he added.
India currently employs more than 10,000 IC design engineers, working in both innovative, homegrown startups, and multinational corporations such as Intel, TI, Cisco, ST, and many others. Sequence has a growing customer base of multinational semiconductor companies in India, particularly in Bangalore's technology-rich environment, and has recently expanded its Center of Excellence in Noida's Logix Techno Park.