STMicroelectronics launches advances in design methodologies
By siliconindia   |   Monday, 27 July 2009, 18:10 IST   |    1 Comments
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STMicroelectronics launches advances in design methodologies
Bangalore: STMicroelectronics (ST), a semiconductor company has unveiled new advances in design methodologies and automation in the areas of 3D stacking for complex System-on-Chip (SoC) ICs, physical and system level chip design and IC reliability. The company also announced that it will participate as presenter or co-author of several papers at the Design Automation Conference (DAC) 2009 in San Francisco from July 26-31. At the DAC 2009 'Management Day' session, Philippe Magarshack, ST's General Manager of Central CAD and Design Solutions will present: '3D Stacking: Opportunities and Trends for Consumer SOCs'. The presentation will discuss 3D integration as a promising technology to extend the momentum of Moore's Law into the next decade, offering higher transistor density, faster interconnects, heterogeneous technology integration, with potentially lower power, cost and faster time-to-market. The presentation will also discuss on the challenges faced in 3D integration. Magarshack will also participate on the panel 'Making Critical Decisions for Emerging SoC Development', which will discuss emerging solutions for complex nanometer SoCs and their economic impact. ST is also presenting several papers in physical and system-level design, including the examination of architectural-level design and power-estimation techniques, and the design-automation of IP re-use.

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