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Cadence, IBM to develop integration-optimized IP
By siliconindia
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Wednesday, 26 May 2010, 18:07 IST |
2 Comments
Bangalore: Cadence Design Systems, an electronic design automation (EDA) software and engineering services firm announced a joint development agreement with IBM to create an integration-optimized IP. The companies claim that this IP can help customers deliver leading-edge designs while reducing the risk and time associated with integrating complex SoC Designs.
Under the agreement, the companies will develop DDR PHYs, memory controllers, and protocols such as PCIe and Ethernet under 32-nanometer silicon-on-insulator. The technology will be used in servers, video games and other devices and will be available through the newly announced Cadence Open Integration Platform.
A core component of its EDA360 vision, the Cadence Open Integration Platform comprises an integration design environment, integration-optimized IP and on-demand integration services, all facilitated by Cadence's mixed-signal and digital design, verification and implementation technologies.
"Qualifying and integrating complex IP is a costly and growing burden for many of our customers," said Vishal Kapoor, Vice President, Product Management of Cadence. "We look forward to teaming with IBM to relieve some of that burden for engineering teams as they grapple with SoCs and systems that will only continue to grow in size and complexity."