Berkeley Design Automation's circuit simulator for Japanese Supercomputer Project

By siliconindia   |   Friday, 22 February 2008, 17:05 IST
Printer Print Email Email
Santa Clara: Berkeley Design Automation, a provider of Precision Circuit Analysis technology for advanced analog and RF integrated circuits (ICs), has announced that the company's Analog FastSPICE circuit simulator has been selected for complex analog and mixed-signal block verification in a 45nm supercomputer chip developed by the University of Tokyo and RIKEN. "Berkeley Design Automation verification tools are critical to the success of our next generation 45nm supercomputer project. Since we cannot rely on digital fastSPICE approximations for these designs, Analog FastSPICE enables us to perform verification tasks that were previously impossible," said Professor Takashi Ikegami of the University of Tokyo. Berkeley Design Automation tools include Analog FastSPICE circuit simulation, RF FastSPICE periodic analyzer, and PLL Noise Analyzer. The company guarantees identical waveforms to the leading "golden" SPICE simulators down to noise floor, while delivering 5x-10x higher performance and 5x-10x higher capacity. Design teams from top 10 semiconductor companies to leading startups use Berkeley Design Automation tools to solve big analog / RF verification problems. Typical applications include characterizing complex blocks and running performance simulation of full circuits (e.g., wireless transceivers, wireline transceivers, high-speed I/O macros, memories, microcontrollers, data converters, and power converters).

siliconindia