Altera unveils enhancements for 28-nm FPGAs

By siliconindia   |   Thursday, 04 February 2010, 18:01 IST
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San Jose: Altera Corporation has announced new enhancements that will be incorporated into the upcoming 28-nanometer FPGAs. Embedded HardCopy Blocks, a new method for partial reconfiguration and embedded 28-Gbps transceivers, which the company claims will improve the density and I/O performance of next-generation Altera FPGAs and further strengthen their competitive position versus ASICs and ASSPs. The rapid growth of bandwidth-intensive applications such as high-definition (HD) video, cloud computing, online data storage and mobile video has created a challenge for both infrastructure and end-user equipment developers. "As we move to the next process node, these new innovations from Altera will take the industry beyond the benefits of Moore's Law to solve bandwidth challenges while staying within cost and power requirements," John Daane, President, Chairman and CEO of Altera. The new Embedded HardCopy Blocks are customizable hard intellectual property (IP) blocks that leverage Altera's HardCopy ASIC capabilities. They are used to harden standard or logic-intensive functions such as interface protocols, application-specific functions, and proprietary custom IP. Partial reconfiguration allows designers to reconfigure part of the FPGA while other sections remain running. This is extremely important in systems where uptime is critical because it allows designers to make updates or adjust functionality without disrupting services. Altera is simplifying the partial reconfiguration process by building the capability on top of the proven incremental compile design flow in its Quartus II design software. Altera has developed 28-Gbps embedded transceivers, which will also be implemented in upcoming 28-nm FPGAs.