Nanoscale process to help computers run faster, better
Monday, 29 September 2008, 20:51 Hrs
Washington: A new nanotechnology will help make computers much smaller, faster and more efficient.
A team led by Craig Hawker, materials professor at California University Santa Barbara, (UCSB) with professors Glenn Fredrickson and Edward J. Kramer, has developed a novel process for creating features on silicon wafers that are between five and 20 nanometres thick. (A nanometre is as thin as a thousandth of human hair).
The new process has been described in Science Express, the online version of Science.
Hawker explained that "if you can shrink all these things down, you get both. You get power and energy efficiency in one package."
He said that the computer industry is up against Moore's law, a trend that Gordon Moore, Intel co-founder, first described in 1965 in which the power of the microprocessor doubles every 18 months, according to an University of California statement.
"One of the problems is that the industry is now running into physical limitations," said Hawker. "You can't shrink things down any more with the current technology."
One of the ways that microprocessors are made is by using a top-down technique called photolithography, which involves shining light onto the surface of a silicon wafer, and making patterns.
He explained that the size of the wavelength of light is becoming a limiting factor, and so his team has invented a new way of creating smaller patterns.
"We've come up with this new blending approach, called block co-polymer lithography, or BCP," said Hawker. "It essentially relies on a natural self-assembly process. Just like proteins in the body, these molecules come together and self assemble into a pattern. And so we use that pattern as our lithographic tool, to make patterns on the silicon wafer."
Using this technique, the size of the features is about the same as that of the molecules. They are very small, between five and 20 nanometres. "With this strategy, we can make many more features," said Hawker, "and hence we can pack the transistors closer together and everything else closer together - using this new form of lithography."
Five leading manufacturers, including Intel and IBM, helped fund the research at UCSB, along with the National Science Foundation and other funders. The university has already applied for patents on the new methods developed here, and it will retain ownership.
Source: IANS
A team led by Craig Hawker, materials professor at California University Santa Barbara, (UCSB) with professors Glenn Fredrickson and Edward J. Kramer, has developed a novel process for creating features on silicon wafers that are between five and 20 nanometres thick. (A nanometre is as thin as a thousandth of human hair).
The new process has been described in Science Express, the online version of Science.
Hawker explained that "if you can shrink all these things down, you get both. You get power and energy efficiency in one package."
He said that the computer industry is up against Moore's law, a trend that Gordon Moore, Intel co-founder, first described in 1965 in which the power of the microprocessor doubles every 18 months, according to an University of California statement.
"One of the problems is that the industry is now running into physical limitations," said Hawker. "You can't shrink things down any more with the current technology."
One of the ways that microprocessors are made is by using a top-down technique called photolithography, which involves shining light onto the surface of a silicon wafer, and making patterns.
He explained that the size of the wavelength of light is becoming a limiting factor, and so his team has invented a new way of creating smaller patterns.
"We've come up with this new blending approach, called block co-polymer lithography, or BCP," said Hawker. "It essentially relies on a natural self-assembly process. Just like proteins in the body, these molecules come together and self assemble into a pattern. And so we use that pattern as our lithographic tool, to make patterns on the silicon wafer."
Using this technique, the size of the features is about the same as that of the molecules. They are very small, between five and 20 nanometres. "With this strategy, we can make many more features," said Hawker, "and hence we can pack the transistors closer together and everything else closer together - using this new form of lithography."
Five leading manufacturers, including Intel and IBM, helped fund the research at UCSB, along with the National Science Foundation and other funders. The university has already applied for patents on the new methods developed here, and it will retain ownership.
Source: IANS
Don't Miss
Write your comment now
|
Submit your news/press release
Let our editorial department know about any news about your company, your
organization, or yourself, or any press release that you have. If we find it suitable for our audience, we will contact you and make a news. Please
also share any links for the news.
- Software Testing is Dead!!!
- Why is Priyanka Gandhi Liked More than Rahul Gandhi?
- Selective Abortion on the Rise among Indians in North America
- Meet the Role Models of Indian Youth
- India's Most Wanted: Pak's Political Hero
- World's Greatest Introverts and Extroverts
- 5 Best Android Smartphones Under Rs.10,000
Beautiful and dress selection, please go to Dresses
| Plan on visiting the Lotus Temple? Get Great Deals on Delhi Hotels ! |
Buy India Wholesale Products on DHgate.com
SPOTLIGHT
Technology
Its time to rejoice for techies this year with technology booming like no other sector.
..